Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	615460153	3679661	0	0
gen_wmask[1].MaskCheckPortA_A	615460153	3679661	0	0
gen_wmask[2].MaskCheckPortA_A	615460153	3679661	0	0
gen_wmask[3].MaskCheckPortA_A	615460153	3679661	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615460153	3679661	0	0
T1	452015	6648	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1077	0	0
T6	1587529	14939	0	0
T7	19809	832	0	0
T8	287070	832	0	0
T9	19131	175	0	0
T10	7154	166	0	0
T11	506853	11177	0	0
T12	108175	832	0	0
T13	0	16745	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615460153	3679661	0	0
T1	452015	6648	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1077	0	0
T6	1587529	14939	0	0
T7	19809	832	0	0
T8	287070	832	0	0
T9	19131	175	0	0
T10	7154	166	0	0
T11	506853	11177	0	0
T12	108175	832	0	0
T13	0	16745	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615460153	3679661	0	0
T1	452015	6648	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1077	0	0
T6	1587529	14939	0	0
T7	19809	832	0	0
T8	287070	832	0	0
T9	19131	175	0	0
T10	7154	166	0	0
T11	506853	11177	0	0
T12	108175	832	0	0
T13	0	16745	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	615460153	3679661	0	0
T1	452015	6648	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1077	0	0
T6	1587529	14939	0	0
T7	19809	832	0	0
T8	287070	832	0	0
T9	19131	175	0	0
T10	7154	166	0	0
T11	506853	11177	0	0
T12	108175	832	0	0
T13	0	16745	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	453596559	2294259	0	0
gen_wmask[1].MaskCheckPortA_A	453596559	2294259	0	0
gen_wmask[2].MaskCheckPortA_A	453596559	2294259	0	0
gen_wmask[3].MaskCheckPortA_A	453596559	2294259	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2294259	0	0
T1	116757	4160	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	832	0	0
T6	797620	7635	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	47	0	0
T10	4759	14	0	0
T11	0	5824	0	0
T12	0	832	0	0
T13	0	11321	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2294259	0	0
T1	116757	4160	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	832	0	0
T6	797620	7635	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	47	0	0
T10	4759	14	0	0
T11	0	5824	0	0
T12	0	832	0	0
T13	0	11321	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2294259	0	0
T1	116757	4160	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	832	0	0
T6	797620	7635	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	47	0	0
T10	4759	14	0	0
T11	0	5824	0	0
T12	0	832	0	0
T13	0	11321	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2294259	0	0
T1	116757	4160	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	832	0	0
T6	797620	7635	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	47	0	0
T10	4759	14	0	0
T11	0	5824	0	0
T12	0	832	0	0
T13	0	11321	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	161863594	1385402	0	0
gen_wmask[1].MaskCheckPortA_A	161863594	1385402	0	0
gen_wmask[2].MaskCheckPortA_A	161863594	1385402	0	0
gen_wmask[3].MaskCheckPortA_A	161863594	1385402	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	1385402	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	7304	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	128	0	0
T10	2395	152	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	5424	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	1385402	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	7304	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	128	0	0
T10	2395	152	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	5424	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	1385402	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	7304	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	128	0	0
T10	2395	152	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	5424	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	1385402	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	7304	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	128	0	0
T10	2395	152	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	5424	0	0
T14	0	10867	0	0
T24	0	979	0	0
T25	0	3943	0	0