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Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[0].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[1].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 gen_dfifo[2].fifo_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 456412406 3147638 0 0
DepthKnown_A 456412406 456283864 0 0
RvalidKnown_A 456412406 456283864 0 0
WreadyKnown_A 456412406 456283864 0 0
gen_passthru_fifo.paramCheckPass 1131 1131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 3147638 0 0
T1 116757 7491 0 0
T2 998 0 0 0
T3 2939 0 0 0
T4 5169 0 0 0
T5 162976 1663 0 0
T6 797620 8317 0 0
T7 14540 1663 0 0
T8 240303 832 0 0
T9 16114 0 0 0
T10 4759 0 0 0
T11 0 9148 0 0
T12 0 832 0 0
T13 0 15816 0 0
T14 0 14984 0 0
T15 0 1671 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1131 1131 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 456412406 3588187 0 0
DepthKnown_A 456412406 456283864 0 0
RvalidKnown_A 456412406 456283864 0 0
WreadyKnown_A 456412406 456283864 0 0
gen_passthru_fifo.paramCheckPass 1131 1131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 3588187 0 0
T1 116757 7083 0 0
T2 998 0 0 0
T3 2939 0 0 0
T4 5169 0 0 0
T5 162976 832 0 0
T6 797620 5824 0 0
T7 14540 832 0 0
T8 240303 832 0 0
T9 16114 0 0 0
T10 4759 0 0 0
T11 0 5824 0 0
T12 0 832 0 0
T13 0 31308 0 0
T14 0 31719 0 0
T15 0 841 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1131 1131 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 456412406 209744 0 0
DepthKnown_A 456412406 456283864 0 0
RvalidKnown_A 456412406 456283864 0 0
WreadyKnown_A 456412406 456283864 0 0
gen_passthru_fifo.paramCheckPass 1131 1131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 209744 0 0
T1 116757 257 0 0
T2 998 0 0 0
T3 2939 0 0 0
T4 5169 0 0 0
T5 162976 60 0 0
T6 797620 1236 0 0
T7 14540 0 0 0
T8 240303 0 0 0
T9 16114 33 0 0
T10 4759 39 0 0
T11 0 386 0 0
T13 0 700 0 0
T14 0 1766 0 0
T24 0 254 0 0
T25 0 886 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1131 1131 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 456412406 480178 0 0
DepthKnown_A 456412406 456283864 0 0
RvalidKnown_A 456412406 456283864 0 0
WreadyKnown_A 456412406 456283864 0 0
gen_passthru_fifo.paramCheckPass 1131 1131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 480178 0 0
T1 116757 1129 0 0
T2 998 0 0 0
T3 2939 0 0 0
T4 5169 0 0 0
T5 162976 60 0 0
T6 797620 1236 0 0
T7 14540 0 0 0
T8 240303 0 0 0
T9 16114 33 0 0
T10 4759 39 0 0
T11 0 386 0 0
T13 0 3255 0 0
T14 0 7690 0 0
T24 0 254 0 0
T25 0 3615 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1131 1131 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 456412406 6176424 0 0
DepthKnown_A 456412406 456283864 0 0
RvalidKnown_A 456412406 456283864 0 0
WreadyKnown_A 456412406 456283864 0 0
gen_passthru_fifo.paramCheckPass 1131 1131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 6176424 0 0
T1 116757 496 0 0
T2 998 21 0 0
T3 2939 1 0 0
T4 5169 32 0 0
T5 162976 294 0 0
T6 797620 18264 0 0
T7 14540 664 0 0
T8 240303 8827 0 0
T9 16114 3745 0 0
T10 4759 936 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1131 1131 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable


Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 456412406 12307400 0 0
DepthKnown_A 456412406 456283864 0 0
RvalidKnown_A 456412406 456283864 0 0
WreadyKnown_A 456412406 456283864 0 0
gen_passthru_fifo.paramCheckPass 1131 1131 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 12307400 0 0
T1 116757 1988 0 0
T2 998 21 0 0
T3 2939 1 0 0
T4 5169 191 0 0
T5 162976 293 0 0
T6 797620 18137 0 0
T7 14540 663 0 0
T8 240303 8826 0 0
T9 16114 3745 0 0
T10 4759 936 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 456412406 456283864 0 0
T1 116757 116704 0 0
T2 998 928 0 0
T3 2939 2107 0 0
T4 5169 5078 0 0
T5 162976 162892 0 0
T6 797620 797569 0 0
T7 14540 14461 0 0
T8 240303 240249 0 0
T9 16114 16014 0 0
T10 4759 4672 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 1131 1131 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%