Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T10
1	0	Covered	T6,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Unreachable
1	1	Covered	T6,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	777323747	613914242	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	777323747	4107812	0	0
GntImpliesValid_A	777323747	4107812	0	0
GrantKnown_A	777323747	613914242	0	0
IdxKnown_A	777323747	613914242	0	0
IndexIsCorrect_A	777323747	4107812	0	0
LockArbDecision_A	777323747	0	0	0
NoReadyValidNoGrant_A	777323747	0	0	0
ReadyAndValidImplyGrant_A	777323747	4107812	0	0
ReqAndReadyImplyGrant_A	777323747	4107812	0	0
ReqImpliesValid_A	777323747	4107812	0	0
ReqStaysHighUntilGranted0_M	777323747	0	0	0
RoundRobin_A	777323747	9	0	956
ValidKnown_A	777323747	613914242	0	0
gen_data_port_assertion.DataFlow_A	777323747	4107812	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	613914242	0	0
T1	452015	450807	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	6609	5798	0	0
T5	226212	194495	0	0
T6	2377438	1581360	0	0
T7	25078	18877	0	0
T8	333837	286645	0	0
T9	22148	19006	0	0
T10	9549	6888	0	0
T11	1013706	505508	0	0
T12	216350	108122	0	0
T13	895658	888115	0	0
T14	0	615305	0	0
T15	0	113084	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	613914242	0	0
T1	452015	450807	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	6609	5798	0	0
T5	226212	194495	0	0
T6	2377438	1581360	0	0
T7	25078	18877	0	0
T8	333837	286645	0	0
T9	22148	19006	0	0
T10	9549	6888	0	0
T11	1013706	505508	0	0
T12	216350	108122	0	0
T13	895658	888115	0	0
T14	0	615305	0	0
T15	0	113084	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	613914242	0	0
T1	452015	450807	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	6609	5798	0	0
T5	226212	194495	0	0
T6	2377438	1581360	0	0
T7	25078	18877	0	0
T8	333837	286645	0	0
T9	22148	19006	0	0
T10	9549	6888	0	0
T11	1013706	505508	0	0
T12	216350	108122	0	0
T13	895658	888115	0	0
T14	0	615305	0	0
T15	0	113084	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	9	0	956
T39	577732	1	0	1
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	107424	0	0	1
T47	38650	0	0	1
T48	18385	0	0	1
T49	521138	0	0	1
T50	2105	0	0	1
T51	148455	0	0	1
T52	795	0	0	1
T53	190784	0	0	1
T54	108611	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	613914242	0	0
T1	452015	450807	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	6609	5798	0	0
T5	226212	194495	0	0
T6	2377438	1581360	0	0
T7	25078	18877	0	0
T8	333837	286645	0	0
T9	22148	19006	0	0
T10	9549	6888	0	0
T11	1013706	505508	0	0
T12	216350	108122	0	0
T13	895658	888115	0	0
T14	0	615305	0	0
T15	0	113084	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	777323747	4107812	0	0
T1	452015	6915	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5889	0	0	0
T5	194594	1140	0	0
T6	2377438	18176	0	0
T7	25078	832	0	0
T8	333837	832	0	0
T9	22148	257	0	0
T10	9549	223	0	0
T11	1013706	11578	0	0
T12	216350	832	0	0
T13	895658	18031	0	0
T14	624139	12929	0	0
T15	113206	0	0	0
T16	0	13764	0	0
T24	0	1189	0	0
T25	0	5010	0	0
T26	0	3892	0	0
T30	0	6253	0	0
T34	0	9	0	0
T38	0	84	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T9,T10
1	0	Covered	T6,T9,T10

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T9
1	0	Unreachable
1	1	Covered	T6,T9,T10

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T9,T10
0	0	1	Unreachable
0	0	0	Covered	T4,T6,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	161863594	32040765	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	161863594	694345	0	0
GntImpliesValid_A	161863594	694345	0	0
GrantKnown_A	161863594	32040765	0	0
IdxKnown_A	161863594	32040765	0	0
IndexIsCorrect_A	161863594	694345	0	0
LockArbDecision_A	161863594	0	0	0
NoReadyValidNoGrant_A	161863594	0	0	0
ReadyAndValidImplyGrant_A	161863594	694345	0	0
ReqAndReadyImplyGrant_A	161863594	694345	0	0
ReqImpliesValid_A	161863594	694345	0	0
ReqStaysHighUntilGranted0_M	161863594	0	0	0
RoundRobin_A	161863594	0	0	0
ValidKnown_A	161863594	32040765	0	0
gen_data_port_assertion.DataFlow_A	161863594	694345	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	32040765	0	0
T4	720	720	0	0
T5	31618	0	0	0
T6	789909	216368	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	2992	0	0
T10	2395	2216	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	67280	0	0
T14	0	142016	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	32040765	0	0
T4	720	720	0	0
T5	31618	0	0	0
T6	789909	216368	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	2992	0	0
T10	2395	2216	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	67280	0	0
T14	0	142016	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	32040765	0	0
T4	720	720	0	0
T5	31618	0	0	0
T6	789909	216368	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	2992	0	0
T10	2395	2216	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	67280	0	0
T14	0	142016	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	32040765	0	0
T4	720	720	0	0
T5	31618	0	0	0
T6	789909	216368	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	2992	0	0
T10	2395	2216	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	67280	0	0
T14	0	142016	0	0
T16	0	303552	0	0
T24	0	21064	0	0
T25	0	72264	0	0
T26	0	100472	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	694345	0	0
T6	789909	6072	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	177	0	0
T10	2395	170	0	0
T11	506853	0	0	0
T12	108175	0	0	0
T13	895658	2392	0	0
T14	624139	5179	0	0
T15	113206	0	0	0
T16	0	5547	0	0
T24	0	1189	0	0
T25	0	3202	0	0
T26	0	3892	0	0
T38	0	84	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T6
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	161863594	128362537	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	161863594	919863	0	0
GntImpliesValid_A	161863594	919863	0	0
GrantKnown_A	161863594	128362537	0	0
IdxKnown_A	161863594	128362537	0	0
IndexIsCorrect_A	161863594	919863	0	0
LockArbDecision_A	161863594	0	0	0
NoReadyValidNoGrant_A	161863594	0	0	0
ReadyAndValidImplyGrant_A	161863594	919863	0	0
ReqAndReadyImplyGrant_A	161863594	919863	0	0
ReqImpliesValid_A	161863594	919863	0	0
ReqStaysHighUntilGranted0_M	161863594	0	0	0
RoundRobin_A	161863594	0	0	0
ValidKnown_A	161863594	128362537	0	0
gen_data_port_assertion.DataFlow_A	161863594	919863	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	128362537	0	0
T1	335258	334103	0	0
T4	720	0	0	0
T5	31618	31603	0	0
T6	789909	567423	0	0
T7	5269	4416	0	0
T8	46767	46396	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	505508	0	0
T12	108175	108122	0	0
T13	0	820835	0	0
T14	0	473289	0	0
T15	0	113084	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	128362537	0	0
T1	335258	334103	0	0
T4	720	0	0	0
T5	31618	31603	0	0
T6	789909	567423	0	0
T7	5269	4416	0	0
T8	46767	46396	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	505508	0	0
T12	108175	108122	0	0
T13	0	820835	0	0
T14	0	473289	0	0
T15	0	113084	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	128362537	0	0
T1	335258	334103	0	0
T4	720	0	0	0
T5	31618	31603	0	0
T6	789909	567423	0	0
T7	5269	4416	0	0
T8	46767	46396	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	505508	0	0
T12	108175	108122	0	0
T13	0	820835	0	0
T14	0	473289	0	0
T15	0	113084	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	128362537	0	0
T1	335258	334103	0	0
T4	720	0	0	0
T5	31618	31603	0	0
T6	789909	567423	0	0
T7	5269	4416	0	0
T8	46767	46396	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	505508	0	0
T12	108175	108122	0	0
T13	0	820835	0	0
T14	0	473289	0	0
T15	0	113084	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161863594	919863	0	0
T1	335258	2488	0	0
T4	720	0	0	0
T5	31618	245	0	0
T6	789909	3222	0	0
T7	5269	0	0	0
T8	46767	0	0	0
T9	3017	0	0	0
T10	2395	0	0	0
T11	506853	5353	0	0
T12	108175	0	0	0
T13	0	3584	0	0
T14	0	7750	0	0
T16	0	8217	0	0
T25	0	1808	0	0
T30	0	6253	0	0
T34	0	9	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T5,T6

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T5,T6
1	0	Covered	T1,T5,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T5,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T5,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T5,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	453596559	453510940	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	453596559	2493604	0	0
GntImpliesValid_A	453596559	2493604	0	0
GrantKnown_A	453596559	453510940	0	0
IdxKnown_A	453596559	453510940	0	0
IndexIsCorrect_A	453596559	2493604	0	0
LockArbDecision_A	453596559	0	0	0
NoReadyValidNoGrant_A	453596559	0	0	0
ReadyAndValidImplyGrant_A	453596559	2493604	0	0
ReqAndReadyImplyGrant_A	453596559	2493604	0	0
ReqImpliesValid_A	453596559	2493604	0	0
ReqStaysHighUntilGranted0_M	453596559	0	0	0
RoundRobin_A	453596559	9	0	956
ValidKnown_A	453596559	453510940	0	0
gen_data_port_assertion.DataFlow_A	453596559	2493604	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	453510940	0	0
T1	116757	116704	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	5169	5078	0	0
T5	162976	162892	0	0
T6	797620	797569	0	0
T7	14540	14461	0	0
T8	240303	240249	0	0
T9	16114	16014	0	0
T10	4759	4672	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	453510940	0	0
T1	116757	116704	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	5169	5078	0	0
T5	162976	162892	0	0
T6	797620	797569	0	0
T7	14540	14461	0	0
T8	240303	240249	0	0
T9	16114	16014	0	0
T10	4759	4672	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	453510940	0	0
T1	116757	116704	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	5169	5078	0	0
T5	162976	162892	0	0
T6	797620	797569	0	0
T7	14540	14461	0	0
T8	240303	240249	0	0
T9	16114	16014	0	0
T10	4759	4672	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	9	0	956
T39	577732	1	0	1
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	107424	0	0	1
T47	38650	0	0	1
T48	18385	0	0	1
T49	521138	0	0	1
T50	2105	0	0	1
T51	148455	0	0	1
T52	795	0	0	1
T53	190784	0	0	1
T54	108611	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	453510940	0	0
T1	116757	116704	0	0
T2	998	928	0	0
T3	2939	2107	0	0
T4	5169	5078	0	0
T5	162976	162892	0	0
T6	797620	797569	0	0
T7	14540	14461	0	0
T8	240303	240249	0	0
T9	16114	16014	0	0
T10	4759	4672	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453596559	2493604	0	0
T1	116757	4427	0	0
T2	998	0	0	0
T3	2939	0	0	0
T4	5169	0	0	0
T5	162976	895	0	0
T6	797620	8882	0	0
T7	14540	832	0	0
T8	240303	832	0	0
T9	16114	80	0	0
T10	4759	53	0	0
T11	0	6225	0	0
T12	0	832	0	0
T13	0	12055	0	0