Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3975852	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4389515

1

T2

1263

T3

1849

T5

125

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4595469	1			T1	57		T2	785		T3	1932
values[0x0]	1884010	1			T2	450		T3	440		T4	1
values[0x1]	1885888	1			T2	431		T3	463		T4	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2801619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5563748

1

T1

18

T2

1349

T3

2053

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	32879	1			T2	8		T5	1		T6	21
valid_sources[0x01]	28423	1			T2	5		T6	14		T10	3
valid_sources[0x02]	31438	1			T2	9		T6	13		T10	5
valid_sources[0x03]	33192	1			T2	5		T5	1		T6	11
valid_sources[0x04]	30033	1			T2	5		T6	14		T10	2
valid_sources[0x05]	34311	1			T2	4		T5	2		T6	14
valid_sources[0x06]	30256	1			T2	7		T5	1		T6	16
valid_sources[0x07]	35863	1			T2	14		T6	14		T10	5
valid_sources[0x08]	30774	1			T2	2		T6	9		T10	12
valid_sources[0x09]	32491	1			T2	7		T5	1		T6	7
valid_sources[0x0a]	32677	1			T2	6		T5	1		T6	15
valid_sources[0x0b]	30627	1			T2	4		T6	14		T10	3
valid_sources[0x0c]	29349	1			T2	8		T6	14		T10	10
valid_sources[0x0d]	31042	1			T2	7		T6	14		T10	12
valid_sources[0x0e]	31653	1			T2	6		T6	16		T10	6
valid_sources[0x0f]	32915	1			T2	9		T5	4		T6	13
valid_sources[0x10]	31497	1			T2	5		T5	1		T6	22
valid_sources[0x11]	29928	1			T2	12		T5	3		T6	16
valid_sources[0x12]	30175	1			T2	12		T5	2		T6	17
valid_sources[0x13]	31528	1			T2	6		T5	1		T6	11
valid_sources[0x14]	32808	1			T2	3		T6	14		T10	8
valid_sources[0x15]	31426	1			T2	6		T5	2		T6	20
valid_sources[0x16]	34194	1			T2	7		T6	17		T10	2
valid_sources[0x17]	31407	1			T2	5		T6	17		T10	10
valid_sources[0x18]	32405	1			T2	8		T6	18		T10	9
valid_sources[0x19]	31052	1			T2	4		T5	2		T6	16
valid_sources[0x1a]	34144	1			T2	7		T5	1		T6	12
valid_sources[0x1b]	29715	1			T2	6		T5	1		T6	11
valid_sources[0x1c]	32726	1			T2	4		T6	9		T10	2
valid_sources[0x1d]	34017	1			T2	8		T5	1		T6	12
valid_sources[0x1e]	33135	1			T2	2		T6	12		T10	6
valid_sources[0x1f]	31170	1			T2	3		T5	2		T6	15
valid_sources[0x20]	32471	1			T2	2		T3	1960		T6	17
valid_sources[0x21]	31201	1			T2	8		T5	2		T6	13
valid_sources[0x22]	42340	1			T2	12		T6	12		T10	7
valid_sources[0x23]	36315	1			T2	6		T5	1		T6	11
valid_sources[0x24]	30794	1			T2	6		T6	19		T10	16
valid_sources[0x25]	29457	1			T2	7		T5	2		T6	15
valid_sources[0x26]	31097	1			T2	5		T5	3		T6	9
valid_sources[0x27]	33568	1			T2	4		T6	20		T11	39
valid_sources[0x28]	30817	1			T2	6		T5	2		T6	20
valid_sources[0x29]	39857	1			T2	2		T5	1		T6	14
valid_sources[0x2a]	29822	1			T2	4		T6	17		T10	3
valid_sources[0x2b]	31257	1			T2	5		T6	12		T10	3
valid_sources[0x2c]	30160	1			T2	4		T4	2		T5	1
valid_sources[0x2d]	32092	1			T2	4		T5	1		T6	14
valid_sources[0x2e]	30511	1			T2	4		T5	1		T6	13
valid_sources[0x2f]	30879	1			T2	6		T6	18		T10	5
valid_sources[0x30]	30935	1			T2	6		T5	1		T6	15
valid_sources[0x31]	28372	1			T2	3		T6	12		T10	2
valid_sources[0x32]	32903	1			T2	6		T5	1		T6	15
valid_sources[0x33]	33318	1			T2	7		T5	2		T6	6
valid_sources[0x34]	33159	1			T2	5		T6	21		T10	17
valid_sources[0x35]	29844	1			T2	8		T6	14		T10	6
valid_sources[0x36]	29799	1			T2	4		T6	18		T7	1
valid_sources[0x37]	32371	1			T2	6		T5	1		T6	12
valid_sources[0x38]	29685	1			T2	7		T6	10		T10	14
valid_sources[0x39]	32367	1			T2	10		T6	26		T10	8
valid_sources[0x3a]	33501	1			T2	7		T6	14		T11	34
valid_sources[0x3b]	32348	1			T2	7		T5	1		T6	13
valid_sources[0x3c]	38601	1			T2	6		T6	18		T10	13
valid_sources[0x3d]	31614	1			T2	7		T6	16		T11	39
valid_sources[0x3e]	31612	1			T2	7		T6	20		T10	4
valid_sources[0x3f]	31366	1			T2	7		T4	2		T6	13
valid_sources[0x40]	31079	1			T2	8		T6	14		T10	7
valid_sources[0x41]	30490	1			T2	6		T5	1		T6	10
valid_sources[0x42]	36728	1			T2	8		T6	20		T11	54
valid_sources[0x43]	28736	1			T2	5		T6	21		T10	4
valid_sources[0x44]	29092	1			T2	4		T6	14		T10	3
valid_sources[0x45]	30405	1			T2	7		T5	1		T6	19
valid_sources[0x46]	33402	1			T2	7		T6	16		T10	5
valid_sources[0x47]	31288	1			T2	10		T5	1		T6	8
valid_sources[0x48]	32738	1			T2	5		T5	1		T6	15
valid_sources[0x49]	32022	1			T2	3		T6	14		T10	6
valid_sources[0x4a]	47354	1			T2	7		T6	13		T10	10
valid_sources[0x4b]	33241	1			T2	6		T6	16		T9	882
valid_sources[0x4c]	31747	1			T2	11		T5	1		T6	16
valid_sources[0x4d]	39498	1			T2	4		T6	16		T10	13
valid_sources[0x4e]	33322	1			T2	5		T5	1		T6	12
valid_sources[0x4f]	31721	1			T2	6		T6	9		T10	7
valid_sources[0x50]	30666	1			T2	11		T5	1		T6	13
valid_sources[0x51]	31105	1			T2	9		T5	1		T6	12
valid_sources[0x52]	38153	1			T2	10		T6	15		T10	1
valid_sources[0x53]	31687	1			T2	3		T5	1		T6	21
valid_sources[0x54]	34448	1			T2	4		T6	18		T10	9
valid_sources[0x55]	28404	1			T2	7		T6	14		T10	10
valid_sources[0x56]	31210	1			T2	2		T5	1		T6	17
valid_sources[0x57]	33272	1			T2	5		T5	1		T6	13
valid_sources[0x58]	29598	1			T2	8		T6	16		T10	7
valid_sources[0x59]	31376	1			T2	5		T6	18		T10	9
valid_sources[0x5a]	30048	1			T2	8		T6	11		T10	3
valid_sources[0x5b]	32293	1			T2	9		T6	12		T10	12
valid_sources[0x5c]	29291	1			T2	7		T6	17		T7	1
valid_sources[0x5d]	35903	1			T2	6		T6	19		T11	49
valid_sources[0x5e]	29541	1			T2	5		T5	1		T6	13
valid_sources[0x5f]	32561	1			T2	6		T3	1		T6	15
valid_sources[0x60]	31381	1			T2	10		T6	12		T11	40
valid_sources[0x61]	32073	1			T2	9		T6	16		T10	5
valid_sources[0x62]	31130	1			T2	4		T5	1		T6	16
valid_sources[0x63]	34914	1			T2	10		T6	13		T10	6
valid_sources[0x64]	34322	1			T2	6		T6	13		T11	47
valid_sources[0x65]	34030	1			T2	5		T6	15		T10	14
valid_sources[0x66]	33947	1			T2	8		T6	20		T10	1
valid_sources[0x67]	33591	1			T2	3		T6	8		T10	3
valid_sources[0x68]	31258	1			T2	5		T6	9		T10	7
valid_sources[0x69]	31311	1			T2	4		T6	13		T10	4
valid_sources[0x6a]	31119	1			T2	3		T5	4		T6	15
valid_sources[0x6b]	33123	1			T2	4		T6	16		T10	12
valid_sources[0x6c]	33366	1			T2	4		T6	13		T10	13
valid_sources[0x6d]	32562	1			T2	1		T6	17		T11	47
valid_sources[0x6e]	30706	1			T2	7		T6	11		T10	5
valid_sources[0x6f]	32379	1			T2	7		T6	17		T10	6
valid_sources[0x70]	30827	1			T2	8		T6	7		T10	6
valid_sources[0x71]	35390	1			T2	6		T6	12		T10	5
valid_sources[0x72]	33137	1			T2	6		T5	1		T6	10
valid_sources[0x73]	45889	1			T2	4		T6	20		T10	4
valid_sources[0x74]	31057	1			T2	8		T6	11		T10	14
valid_sources[0x75]	30110	1			T2	4		T6	17		T10	1
valid_sources[0x76]	33298	1			T2	11		T5	1		T6	12
valid_sources[0x77]	32261	1			T2	11		T6	14		T8	452
valid_sources[0x78]	35824	1			T2	11		T5	1		T6	13
valid_sources[0x79]	31613	1			T2	6		T5	1		T6	20
valid_sources[0x7a]	36815	1			T2	6		T6	9		T10	3
valid_sources[0x7b]	34834	1			T2	11		T6	17		T10	10
valid_sources[0x7c]	30622	1			T2	2		T6	18		T10	14
valid_sources[0x7d]	49519	1			T2	11		T5	1		T6	13
valid_sources[0x7e]	32086	1			T2	9		T5	1		T6	12
valid_sources[0x7f]	28697	1			T2	4		T5	1		T6	10
valid_sources[0x80]	30079	1			T2	5		T6	20		T10	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

996205

1

T2

387

T3

953

T5

1

values[0x0]

all_enables

biggest_size

1709469

1

T2

448

T3

439

T5

62

values[0x1]

all_enables

biggest_size

1683841

1

T2

428

T3

457

T5

62