Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3998472

1

T1

57

T2

403

T3

986

full_word

4390754

1

T2

1263

T3

1849

T5

125

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8388796	1			T1	57		T2	1666		T3	2835
auto[TlIntgErrCmd]	126	1			T97	6		T99	6		T100	10
auto[TlIntgErrData]	146	1			T97	13		T99	6		T100	11
auto[TlIntgErrBoth]	158	1			T97	11		T99	8		T100	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4600211

1

T1

57

T2

785

T3

1932

auto[1]

3789015

1

T2

881

T3

903

T4

7

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3603475	1			T1	57		T2	398		T3	979
auto[TlIntgErrNone]	partial	auto[1]	394595	1			T2	5		T3	7		T4	7
auto[TlIntgErrNone]	full_word	auto[0]	996538	1			T2	387		T3	953		T5	1
auto[TlIntgErrNone]	full_word	auto[1]	3394188	1			T2	876		T3	896		T5	124
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T97	2		T99	1		T100	4
auto[TlIntgErrCmd]	partial	auto[1]	67	1			T97	4		T99	5		T100	6
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T252	3		T147	1		T254	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T252	1		T253	1		T255	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T97	8		T99	2		T100	3
auto[TlIntgErrData]	partial	auto[1]	74	1			T97	4		T99	4		T100	7
auto[TlIntgErrData]	full_word	auto[0]	5	1			T97	1		T100	1		T256	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T256	1		T257	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	66	1			T97	5		T99	3		T100	5
auto[TlIntgErrBoth]	partial	auto[1]	80	1			T97	5		T99	4		T100	4
auto[TlIntgErrBoth]	full_word	auto[0]	7	1			T97	1		T145	1		T258	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T99	1		T253	1		T147	1