Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457312026	2907377	0	0
DepthKnown_A	457312026	457176730	0	0
RvalidKnown_A	457312026	457176730	0	0
WreadyKnown_A	457312026	457176730	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	2907377	0	0
T2	20166	1663	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	5821	0	0
T7	1268	0	0	0
T8	4184	1669	0	0
T9	47040	832	0	0
T10	560093	1668	0	0
T11	189404	11644	0	0
T13	0	1664	0	0
T16	0	1663	0	0
T17	0	1343	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457312026	3390599	0	0
DepthKnown_A	457312026	457176730	0	0
RvalidKnown_A	457312026	457176730	0	0
WreadyKnown_A	457312026	457176730	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	3390599	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	839	0	0
T9	47040	832	0	0
T10	560093	837	0	0
T11	189404	8320	0	0
T13	0	833	0	0
T16	0	832	0	0
T17	0	1088	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457312026	207003	0	0
DepthKnown_A	457312026	457176730	0	0
RvalidKnown_A	457312026	457176730	0	0
WreadyKnown_A	457312026	457176730	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	207003	0	0
T11	189404	400	0	0
T12	193454	0	0	0
T13	756482	835	0	0
T14	4027	0	0	0
T15	1318	0	0	0
T16	83847	309	0	0
T17	133913	0	0	0
T25	222596	0	0	0
T26	3152	3	0	0
T27	1354	0	0	0
T36	0	288	0	0
T37	0	448	0	0
T38	0	626	0	0
T39	0	825	0	0
T40	0	192	0	0
T41	0	1709	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457312026	485315	0	0
DepthKnown_A	457312026	457176730	0	0
RvalidKnown_A	457312026	457176730	0	0
WreadyKnown_A	457312026	457176730	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	485315	0	0
T11	189404	400	0	0
T12	193454	0	0	0
T13	756482	3832	0	0
T14	4027	0	0	0
T15	1318	0	0	0
T16	83847	309	0	0
T17	133913	0	0	0
T25	222596	0	0	0
T26	3152	3	0	0
T27	1354	0	0	0
T36	0	1280	0	0
T37	0	1378	0	0
T38	0	626	0	0
T39	0	3512	0	0
T40	0	192	0	0
T41	0	1702	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457312026	6734051	0	0
DepthKnown_A	457312026	457176730	0	0
RvalidKnown_A	457312026	457176730	0	0
WreadyKnown_A	457312026	457176730	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	6734051	0	0
T1	1244	57	0	0
T2	20166	834	0	0
T3	51592	2004	0	0
T4	1029	8	0	0
T5	120473	149	0	0
T6	139975	384	0	0
T7	1268	3	0	0
T8	4184	47	0	0
T9	47040	50	0	0
T10	560093	872	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	457312026	14959899	0	0
DepthKnown_A	457312026	457176730	0	0
RvalidKnown_A	457312026	457176730	0	0
WreadyKnown_A	457312026	457176730	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	14959899	0	0
T1	1244	235	0	0
T2	20166	834	0	0
T3	51592	2003	0	0
T4	1029	8	0	0
T5	120473	149	0	0
T6	139975	381	0	0
T7	1268	3	0	0
T8	4184	200	0	0
T9	47040	50	0	0
T10	560093	3709	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	457312026	457176730	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0