Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T26
1	0	Covered	T13,T16,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Unreachable
1	1	Covered	T13,T16,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T13,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T16
1	0	Covered	T10,T11,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T10,T11,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T13
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	761522675	606767537	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	761522675	3925585	0	0
GntImpliesValid_A	761522675	3925585	0	0
GrantKnown_A	761522675	606767537	0	0
IdxKnown_A	761522675	606767537	0	0
IndexIsCorrect_A	761522675	3925585	0	0
LockArbDecision_A	761522675	0	0	0
NoReadyValidNoGrant_A	761522675	0	0	0
ReadyAndValidImplyGrant_A	761522675	3925585	0	0
ReqAndReadyImplyGrant_A	761522675	3925585	0	0
ReqImpliesValid_A	761522675	3925585	0	0
ReqStaysHighUntilGranted0_M	761522675	0	0	0
RoundRobin_A	761522675	3	0	956
ValidKnown_A	761522675	606767537	0	0
gen_data_port_assertion.DataFlow_A	761522675	3925585	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	606767537	0	0
T1	1244	1168	0	0
T2	54206	54116	0	0
T3	95485	95152	0	0
T4	1029	979	0	0
T5	151499	134973	0	0
T6	392387	265144	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	126208	86556	0	0
T10	782147	670576	0	0
T11	776328	385984	0	0
T12	49336	22536	0	0
T13	367372	175138	0	0
T14	720	360	0	0
T16	275888	274731	0	0
T17	0	16351	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	606767537	0	0
T1	1244	1168	0	0
T2	54206	54116	0	0
T3	95485	95152	0	0
T4	1029	979	0	0
T5	151499	134973	0	0
T6	392387	265144	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	126208	86556	0	0
T10	782147	670576	0	0
T11	776328	385984	0	0
T12	49336	22536	0	0
T13	367372	175138	0	0
T14	720	360	0	0
T16	275888	274731	0	0
T17	0	16351	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	606767537	0	0
T1	1244	1168	0	0
T2	54206	54116	0	0
T3	95485	95152	0	0
T4	1029	979	0	0
T5	151499	134973	0	0
T6	392387	265144	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	126208	86556	0	0
T10	782147	670576	0	0
T11	776328	385984	0	0
T12	49336	22536	0	0
T13	367372	175138	0	0
T14	720	360	0	0
T16	275888	274731	0	0
T17	0	16351	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3	0	956
T19	0	1	0	0
T41	395494	1	0	1
T44	17286	0	0	1
T50	37714	0	0	1
T57	610384	0	0	1
T58	59360	0	0	1
T59	11826	0	0	1
T60	18331	0	0	1
T61	313863	0	0	1
T63	0	1	0	0
T64	153335	0	0	1
T65	61417	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	606767537	0	0
T1	1244	1168	0	0
T2	54206	54116	0	0
T3	95485	95152	0	0
T4	1029	979	0	0
T5	151499	134973	0	0
T6	392387	265144	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	126208	86556	0	0
T10	782147	670576	0	0
T11	776328	385984	0	0
T12	49336	22536	0	0
T13	367372	175138	0	0
T14	720	360	0	0
T16	275888	274731	0	0
T17	0	16351	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	761522675	3925585	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	671120	840	0	0
T11	577568	11343	0	0
T12	24668	0	0	0
T13	367372	8265	0	0
T14	720	0	0	0
T16	551776	5853	0	0
T17	32702	1088	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	110906	0	0	0
T26	2416	40	0	0
T28	288	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T40	0	1594	0	0
T41	0	10856	0	0
T57	0	1242	0	0
T61	0	2727	0	0
T62	0	3230	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T16,T26
1	0	Covered	T13,T16,T26

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T12,T13
1	0	Unreachable
1	1	Covered	T13,T16,T26

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T13,T16,T26
0	0	1	Unreachable
0	0	0	Covered	T5,T12,T13

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T26
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T13,T16,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153240669	30828141	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153240669	701099	0	0
GntImpliesValid_A	153240669	701099	0	0
GrantKnown_A	153240669	30828141	0	0
IdxKnown_A	153240669	30828141	0	0
IndexIsCorrect_A	153240669	701099	0	0
LockArbDecision_A	153240669	0	0	0
NoReadyValidNoGrant_A	153240669	0	0	0
ReadyAndValidImplyGrant_A	153240669	701099	0	0
ReqAndReadyImplyGrant_A	153240669	701099	0	0
ReqImpliesValid_A	153240669	701099	0	0
ReqStaysHighUntilGranted0_M	153240669	0	0	0
RoundRobin_A	153240669	0	0	0
ValidKnown_A	153240669	30828141	0	0
gen_data_port_assertion.DataFlow_A	153240669	701099	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	30828141	0	0
T5	15513	14560	0	0
T6	126206	0	0	0
T9	39584	0	0	0
T10	111027	0	0	0
T11	388164	0	0	0
T12	24668	22536	0	0
T13	183686	133544	0	0
T14	360	360	0	0
T16	275888	167824	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	30828141	0	0
T5	15513	14560	0	0
T6	126206	0	0	0
T9	39584	0	0	0
T10	111027	0	0	0
T11	388164	0	0	0
T12	24668	22536	0	0
T13	183686	133544	0	0
T14	360	360	0	0
T16	275888	167824	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	30828141	0	0
T5	15513	14560	0	0
T6	126206	0	0	0
T9	39584	0	0	0
T10	111027	0	0	0
T11	388164	0	0	0
T12	24668	22536	0	0
T13	183686	133544	0	0
T14	360	360	0	0
T16	275888	167824	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	30828141	0	0
T5	15513	14560	0	0
T6	126206	0	0	0
T9	39584	0	0	0
T10	111027	0	0	0
T11	388164	0	0	0
T12	24668	22536	0	0
T13	183686	133544	0	0
T14	360	360	0	0
T16	275888	167824	0	0
T25	55453	52792	0	0
T26	0	1208	0	0
T28	0	144	0	0
T29	0	104272	0	0
T30	0	104576	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	701099	0	0
T13	183686	4987	0	0
T14	360	0	0	0
T16	275888	1592	0	0
T17	16351	0	0	0
T18	84	0	0	0
T19	0	2725	0	0
T25	55453	0	0	0
T26	1208	40	0	0
T28	144	0	0	0
T29	108544	0	0	0
T30	110079	0	0	0
T38	0	3543	0	0
T39	0	4715	0	0
T41	0	6645	0	0
T57	0	544	0	0
T61	0	2727	0	0
T62	0	3230	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T13,T16

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T13,T16
1	0	Covered	T10,T11,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T6
1	0	Unreachable
1	1	Covered	T10,T11,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T13,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T10,T11,T13
0	0	1	Unreachable
0	0	0	Covered	T2,T3,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	153240669	120986304	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	153240669	899680	0	0
GntImpliesValid_A	153240669	899680	0	0
GrantKnown_A	153240669	120986304	0	0
IdxKnown_A	153240669	120986304	0	0
IndexIsCorrect_A	153240669	899680	0	0
LockArbDecision_A	153240669	0	0	0
NoReadyValidNoGrant_A	153240669	0	0	0
ReadyAndValidImplyGrant_A	153240669	899680	0	0
ReqAndReadyImplyGrant_A	153240669	899680	0	0
ReqImpliesValid_A	153240669	899680	0	0
ReqStaysHighUntilGranted0_M	153240669	0	0	0
RoundRobin_A	153240669	0	0	0
ValidKnown_A	153240669	120986304	0	0
gen_data_port_assertion.DataFlow_A	153240669	899680	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	120986304	0	0
T2	34040	34040	0	0
T3	43893	43632	0	0
T5	15513	0	0	0
T6	126206	125233	0	0
T9	39584	39584	0	0
T10	111027	110552	0	0
T11	388164	385984	0	0
T12	24668	0	0	0
T13	183686	41594	0	0
T14	360	0	0	0
T16	0	106907	0	0
T17	0	16351	0	0
T18	0	84	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	120986304	0	0
T2	34040	34040	0	0
T3	43893	43632	0	0
T5	15513	0	0	0
T6	126206	125233	0	0
T9	39584	39584	0	0
T10	111027	110552	0	0
T11	388164	385984	0	0
T12	24668	0	0	0
T13	183686	41594	0	0
T14	360	0	0	0
T16	0	106907	0	0
T17	0	16351	0	0
T18	0	84	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	120986304	0	0
T2	34040	34040	0	0
T3	43893	43632	0	0
T5	15513	0	0	0
T6	126206	125233	0	0
T9	39584	39584	0	0
T10	111027	110552	0	0
T11	388164	385984	0	0
T12	24668	0	0	0
T13	183686	41594	0	0
T14	360	0	0	0
T16	0	106907	0	0
T17	0	16351	0	0
T18	0	84	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	120986304	0	0
T2	34040	34040	0	0
T3	43893	43632	0	0
T5	15513	0	0	0
T6	126206	125233	0	0
T9	39584	39584	0	0
T10	111027	110552	0	0
T11	388164	385984	0	0
T12	24668	0	0	0
T13	183686	41594	0	0
T14	360	0	0	0
T16	0	106907	0	0
T17	0	16351	0	0
T18	0	84	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	153240669	899680	0	0
T10	111027	4	0	0
T11	388164	2601	0	0
T12	24668	0	0	0
T13	183686	7	0	0
T14	360	0	0	0
T16	275888	2508	0	0
T17	16351	0	0	0
T25	55453	0	0	0
T26	1208	0	0	0
T28	144	0	0	0
T36	0	3541	0	0
T37	0	5447	0	0
T40	0	1594	0	0
T41	0	4211	0	0
T57	0	698	0	0
T64	0	5900	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T11,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T13
1	0	Covered	T2,T3,T6

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T6

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T6
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T6
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	455041337	454953092	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	455041337	2324806	0	0
GntImpliesValid_A	455041337	2324806	0	0
GrantKnown_A	455041337	454953092	0	0
IdxKnown_A	455041337	454953092	0	0
IndexIsCorrect_A	455041337	2324806	0	0
LockArbDecision_A	455041337	0	0	0
NoReadyValidNoGrant_A	455041337	0	0	0
ReadyAndValidImplyGrant_A	455041337	2324806	0	0
ReqAndReadyImplyGrant_A	455041337	2324806	0	0
ReqImpliesValid_A	455041337	2324806	0	0
ReqStaysHighUntilGranted0_M	455041337	0	0	0
RoundRobin_A	455041337	3	0	956
ValidKnown_A	455041337	454953092	0	0
gen_data_port_assertion.DataFlow_A	455041337	2324806	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	454953092	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	454953092	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	454953092	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	3	0	956
T19	0	1	0	0
T41	395494	1	0	1
T44	17286	0	0	1
T50	37714	0	0	1
T57	610384	0	0	1
T58	59360	0	0	1
T59	11826	0	0	1
T60	18331	0	0	1
T61	313863	0	0	1
T63	0	1	0	0
T64	153335	0	0	1
T65	61417	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	454953092	0	0
T1	1244	1168	0	0
T2	20166	20076	0	0
T3	51592	51520	0	0
T4	1029	979	0	0
T5	120473	120413	0	0
T6	139975	139911	0	0
T7	1268	1200	0	0
T8	4184	4096	0	0
T9	47040	46972	0	0
T10	560093	560024	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455041337	2324806	0	0
T2	20166	832	0	0
T3	51592	832	0	0
T4	1029	0	0	0
T5	120473	0	0	0
T6	139975	3328	0	0
T7	1268	0	0	0
T8	4184	832	0	0
T9	47040	832	0	0
T10	560093	836	0	0
T11	189404	8742	0	0
T13	0	3271	0	0
T16	0	1753	0	0
T17	0	1088	0	0