Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
3186 | 
0 | 
0 | 
| T68 | 
3984 | 
9 | 
0 | 
0 | 
| T70 | 
18693 | 
182 | 
0 | 
0 | 
| T96 | 
3558 | 
109 | 
0 | 
0 | 
| T97 | 
110714 | 
5 | 
0 | 
0 | 
| T98 | 
8172 | 
6 | 
0 | 
0 | 
| T99 | 
19883 | 
4 | 
0 | 
0 | 
| T100 | 
81213 | 
5 | 
0 | 
0 | 
| T101 | 
3652 | 
101 | 
0 | 
0 | 
| T108 | 
5123 | 
10 | 
0 | 
0 | 
| T109 | 
5075 | 
8 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
1952 | 
0 | 
0 | 
| T97 | 
110714 | 
112 | 
0 | 
0 | 
| T103 | 
7861 | 
8 | 
0 | 
0 | 
| T111 | 
10594 | 
3 | 
0 | 
0 | 
| T119 | 
37144 | 
253 | 
0 | 
0 | 
| T145 | 
36359 | 
58 | 
0 | 
0 | 
| T146 | 
66867 | 
69 | 
0 | 
0 | 
| T147 | 
30998 | 
13 | 
0 | 
0 | 
| T148 | 
10352 | 
21 | 
0 | 
0 | 
| T149 | 
3796 | 
2 | 
0 | 
0 | 
| T150 | 
13566 | 
29 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
1972 | 
0 | 
0 | 
| T97 | 
110714 | 
104 | 
0 | 
0 | 
| T119 | 
37144 | 
231 | 
0 | 
0 | 
| T122 | 
180782 | 
440 | 
0 | 
0 | 
| T145 | 
36359 | 
53 | 
0 | 
0 | 
| T146 | 
66867 | 
57 | 
0 | 
0 | 
| T147 | 
30998 | 
4 | 
0 | 
0 | 
| T148 | 
10352 | 
18 | 
0 | 
0 | 
| T149 | 
3796 | 
3 | 
0 | 
0 | 
| T150 | 
13566 | 
24 | 
0 | 
0 | 
| T151 | 
14200 | 
20 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2628 | 
0 | 
0 | 
| T97 | 
110714 | 
202 | 
0 | 
0 | 
| T106 | 
19576 | 
4 | 
0 | 
0 | 
| T111 | 
10594 | 
23 | 
0 | 
0 | 
| T119 | 
37144 | 
244 | 
0 | 
0 | 
| T145 | 
36359 | 
65 | 
0 | 
0 | 
| T146 | 
66867 | 
156 | 
0 | 
0 | 
| T147 | 
30998 | 
45 | 
0 | 
0 | 
| T148 | 
10352 | 
17 | 
0 | 
0 | 
| T150 | 
13566 | 
43 | 
0 | 
0 | 
| T151 | 
14200 | 
38 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
10010 | 
0 | 
0 | 
| T97 | 
110714 | 
2313 | 
0 | 
0 | 
| T111 | 
10594 | 
66 | 
0 | 
0 | 
| T119 | 
37144 | 
230 | 
0 | 
0 | 
| T145 | 
36359 | 
630 | 
0 | 
0 | 
| T146 | 
66867 | 
1359 | 
0 | 
0 | 
| T147 | 
30998 | 
328 | 
0 | 
0 | 
| T148 | 
10352 | 
134 | 
0 | 
0 | 
| T149 | 
3796 | 
57 | 
0 | 
0 | 
| T150 | 
13566 | 
45 | 
0 | 
0 | 
| T151 | 
14200 | 
100 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
11036 | 
0 | 
0 | 
| T97 | 
110714 | 
1914 | 
0 | 
0 | 
| T111 | 
10594 | 
77 | 
0 | 
0 | 
| T119 | 
37144 | 
220 | 
0 | 
0 | 
| T145 | 
36359 | 
739 | 
0 | 
0 | 
| T146 | 
66867 | 
1474 | 
0 | 
0 | 
| T147 | 
30998 | 
403 | 
0 | 
0 | 
| T148 | 
10352 | 
146 | 
0 | 
0 | 
| T149 | 
3796 | 
74 | 
0 | 
0 | 
| T150 | 
13566 | 
42 | 
0 | 
0 | 
| T151 | 
14200 | 
241 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
10271 | 
0 | 
0 | 
| T97 | 
110714 | 
1886 | 
0 | 
0 | 
| T111 | 
10594 | 
171 | 
0 | 
0 | 
| T119 | 
37144 | 
205 | 
0 | 
0 | 
| T122 | 
180782 | 
441 | 
0 | 
0 | 
| T145 | 
36359 | 
443 | 
0 | 
0 | 
| T146 | 
66867 | 
1547 | 
0 | 
0 | 
| T147 | 
30998 | 
382 | 
0 | 
0 | 
| T148 | 
10352 | 
132 | 
0 | 
0 | 
| T150 | 
13566 | 
22 | 
0 | 
0 | 
| T151 | 
14200 | 
174 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
10191 | 
0 | 
0 | 
| T97 | 
110714 | 
2246 | 
0 | 
0 | 
| T111 | 
10594 | 
109 | 
0 | 
0 | 
| T119 | 
37144 | 
223 | 
0 | 
0 | 
| T145 | 
36359 | 
634 | 
0 | 
0 | 
| T146 | 
66867 | 
1023 | 
0 | 
0 | 
| T147 | 
30998 | 
361 | 
0 | 
0 | 
| T148 | 
10352 | 
281 | 
0 | 
0 | 
| T149 | 
3796 | 
8 | 
0 | 
0 | 
| T150 | 
13566 | 
54 | 
0 | 
0 | 
| T151 | 
14200 | 
266 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
9710 | 
0 | 
0 | 
| T97 | 
110714 | 
1477 | 
0 | 
0 | 
| T111 | 
10594 | 
47 | 
0 | 
0 | 
| T119 | 
37144 | 
217 | 
0 | 
0 | 
| T122 | 
180782 | 
483 | 
0 | 
0 | 
| T145 | 
36359 | 
533 | 
0 | 
0 | 
| T146 | 
66867 | 
1334 | 
0 | 
0 | 
| T147 | 
30998 | 
327 | 
0 | 
0 | 
| T148 | 
10352 | 
173 | 
0 | 
0 | 
| T150 | 
13566 | 
38 | 
0 | 
0 | 
| T151 | 
14200 | 
101 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
9005 | 
0 | 
0 | 
| T97 | 
110714 | 
1933 | 
0 | 
0 | 
| T111 | 
10594 | 
107 | 
0 | 
0 | 
| T119 | 
37144 | 
226 | 
0 | 
0 | 
| T145 | 
36359 | 
573 | 
0 | 
0 | 
| T146 | 
66867 | 
1123 | 
0 | 
0 | 
| T147 | 
30998 | 
423 | 
0 | 
0 | 
| T148 | 
10352 | 
169 | 
0 | 
0 | 
| T149 | 
3796 | 
1 | 
0 | 
0 | 
| T150 | 
13566 | 
27 | 
0 | 
0 | 
| T151 | 
14200 | 
140 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
10512 | 
0 | 
0 | 
| T97 | 
110714 | 
2237 | 
0 | 
0 | 
| T111 | 
10594 | 
7 | 
0 | 
0 | 
| T119 | 
37144 | 
260 | 
0 | 
0 | 
| T145 | 
36359 | 
677 | 
0 | 
0 | 
| T146 | 
66867 | 
1336 | 
0 | 
0 | 
| T147 | 
30998 | 
151 | 
0 | 
0 | 
| T148 | 
10352 | 
249 | 
0 | 
0 | 
| T149 | 
3796 | 
59 | 
0 | 
0 | 
| T150 | 
13566 | 
29 | 
0 | 
0 | 
| T151 | 
14200 | 
255 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
9676 | 
0 | 
0 | 
| T97 | 
110714 | 
2298 | 
0 | 
0 | 
| T111 | 
10594 | 
70 | 
0 | 
0 | 
| T119 | 
37144 | 
191 | 
0 | 
0 | 
| T145 | 
36359 | 
500 | 
0 | 
0 | 
| T146 | 
66867 | 
700 | 
0 | 
0 | 
| T147 | 
30998 | 
214 | 
0 | 
0 | 
| T148 | 
10352 | 
132 | 
0 | 
0 | 
| T149 | 
3796 | 
1 | 
0 | 
0 | 
| T150 | 
13566 | 
61 | 
0 | 
0 | 
| T151 | 
14200 | 
371 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5389 | 
0 | 
0 | 
| T97 | 
110714 | 
914 | 
0 | 
0 | 
| T111 | 
10594 | 
44 | 
0 | 
0 | 
| T119 | 
37144 | 
230 | 
0 | 
0 | 
| T145 | 
36359 | 
334 | 
0 | 
0 | 
| T146 | 
66867 | 
517 | 
0 | 
0 | 
| T147 | 
30998 | 
131 | 
0 | 
0 | 
| T148 | 
10352 | 
57 | 
0 | 
0 | 
| T149 | 
3796 | 
12 | 
0 | 
0 | 
| T150 | 
13566 | 
68 | 
0 | 
0 | 
| T151 | 
14200 | 
148 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4712 | 
0 | 
0 | 
| T97 | 
110714 | 
732 | 
0 | 
0 | 
| T111 | 
10594 | 
74 | 
0 | 
0 | 
| T119 | 
37144 | 
174 | 
0 | 
0 | 
| T145 | 
36359 | 
249 | 
0 | 
0 | 
| T146 | 
66867 | 
547 | 
0 | 
0 | 
| T147 | 
30998 | 
134 | 
0 | 
0 | 
| T148 | 
10352 | 
18 | 
0 | 
0 | 
| T149 | 
3796 | 
25 | 
0 | 
0 | 
| T150 | 
13566 | 
10 | 
0 | 
0 | 
| T151 | 
14200 | 
73 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5108 | 
0 | 
0 | 
| T97 | 
110714 | 
604 | 
0 | 
0 | 
| T111 | 
10594 | 
23 | 
0 | 
0 | 
| T119 | 
37144 | 
234 | 
0 | 
0 | 
| T145 | 
36359 | 
344 | 
0 | 
0 | 
| T146 | 
66867 | 
342 | 
0 | 
0 | 
| T147 | 
30998 | 
105 | 
0 | 
0 | 
| T148 | 
10352 | 
62 | 
0 | 
0 | 
| T149 | 
3796 | 
9 | 
0 | 
0 | 
| T150 | 
13566 | 
15 | 
0 | 
0 | 
| T151 | 
14200 | 
78 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5224 | 
0 | 
0 | 
| T97 | 
110714 | 
870 | 
0 | 
0 | 
| T111 | 
10594 | 
54 | 
0 | 
0 | 
| T119 | 
37144 | 
239 | 
0 | 
0 | 
| T145 | 
36359 | 
257 | 
0 | 
0 | 
| T146 | 
66867 | 
308 | 
0 | 
0 | 
| T147 | 
30998 | 
139 | 
0 | 
0 | 
| T148 | 
10352 | 
23 | 
0 | 
0 | 
| T149 | 
3796 | 
26 | 
0 | 
0 | 
| T150 | 
13566 | 
50 | 
0 | 
0 | 
| T151 | 
14200 | 
100 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5112 | 
0 | 
0 | 
| T97 | 
110714 | 
961 | 
0 | 
0 | 
| T111 | 
10594 | 
38 | 
0 | 
0 | 
| T119 | 
37144 | 
222 | 
0 | 
0 | 
| T122 | 
180782 | 
423 | 
0 | 
0 | 
| T145 | 
36359 | 
271 | 
0 | 
0 | 
| T146 | 
66867 | 
484 | 
0 | 
0 | 
| T147 | 
30998 | 
175 | 
0 | 
0 | 
| T148 | 
10352 | 
8 | 
0 | 
0 | 
| T150 | 
13566 | 
20 | 
0 | 
0 | 
| T151 | 
14200 | 
59 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5171 | 
0 | 
0 | 
| T97 | 
110714 | 
965 | 
0 | 
0 | 
| T111 | 
10594 | 
109 | 
0 | 
0 | 
| T119 | 
37144 | 
269 | 
0 | 
0 | 
| T145 | 
36359 | 
223 | 
0 | 
0 | 
| T146 | 
66867 | 
564 | 
0 | 
0 | 
| T147 | 
30998 | 
91 | 
0 | 
0 | 
| T148 | 
10352 | 
23 | 
0 | 
0 | 
| T149 | 
3796 | 
2 | 
0 | 
0 | 
| T150 | 
13566 | 
35 | 
0 | 
0 | 
| T151 | 
14200 | 
81 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4950 | 
0 | 
0 | 
| T97 | 
110714 | 
890 | 
0 | 
0 | 
| T111 | 
10594 | 
81 | 
0 | 
0 | 
| T119 | 
37144 | 
214 | 
0 | 
0 | 
| T145 | 
36359 | 
190 | 
0 | 
0 | 
| T146 | 
66867 | 
317 | 
0 | 
0 | 
| T147 | 
30998 | 
155 | 
0 | 
0 | 
| T148 | 
10352 | 
15 | 
0 | 
0 | 
| T149 | 
3796 | 
2 | 
0 | 
0 | 
| T150 | 
13566 | 
60 | 
0 | 
0 | 
| T151 | 
14200 | 
25 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5482 | 
0 | 
0 | 
| T97 | 
110714 | 
601 | 
0 | 
0 | 
| T111 | 
10594 | 
73 | 
0 | 
0 | 
| T119 | 
37144 | 
262 | 
0 | 
0 | 
| T145 | 
36359 | 
253 | 
0 | 
0 | 
| T146 | 
66867 | 
681 | 
0 | 
0 | 
| T147 | 
30998 | 
150 | 
0 | 
0 | 
| T148 | 
10352 | 
48 | 
0 | 
0 | 
| T149 | 
3796 | 
35 | 
0 | 
0 | 
| T150 | 
13566 | 
31 | 
0 | 
0 | 
| T151 | 
14200 | 
129 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4897 | 
0 | 
0 | 
| T97 | 
110714 | 
989 | 
0 | 
0 | 
| T111 | 
10594 | 
83 | 
0 | 
0 | 
| T119 | 
37144 | 
223 | 
0 | 
0 | 
| T145 | 
36359 | 
173 | 
0 | 
0 | 
| T146 | 
66867 | 
459 | 
0 | 
0 | 
| T147 | 
30998 | 
195 | 
0 | 
0 | 
| T148 | 
10352 | 
20 | 
0 | 
0 | 
| T149 | 
3796 | 
8 | 
0 | 
0 | 
| T150 | 
13566 | 
79 | 
0 | 
0 | 
| T151 | 
14200 | 
27 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5221 | 
0 | 
0 | 
| T97 | 
110714 | 
756 | 
0 | 
0 | 
| T111 | 
10594 | 
37 | 
0 | 
0 | 
| T119 | 
37144 | 
204 | 
0 | 
0 | 
| T122 | 
180782 | 
451 | 
0 | 
0 | 
| T145 | 
36359 | 
244 | 
0 | 
0 | 
| T146 | 
66867 | 
531 | 
0 | 
0 | 
| T147 | 
30998 | 
124 | 
0 | 
0 | 
| T148 | 
10352 | 
108 | 
0 | 
0 | 
| T150 | 
13566 | 
16 | 
0 | 
0 | 
| T151 | 
14200 | 
173 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4400 | 
0 | 
0 | 
| T97 | 
110714 | 
769 | 
0 | 
0 | 
| T111 | 
10594 | 
35 | 
0 | 
0 | 
| T119 | 
37144 | 
254 | 
0 | 
0 | 
| T145 | 
36359 | 
156 | 
0 | 
0 | 
| T146 | 
66867 | 
389 | 
0 | 
0 | 
| T147 | 
30998 | 
174 | 
0 | 
0 | 
| T148 | 
10352 | 
25 | 
0 | 
0 | 
| T149 | 
3796 | 
17 | 
0 | 
0 | 
| T150 | 
13566 | 
37 | 
0 | 
0 | 
| T151 | 
14200 | 
61 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5141 | 
0 | 
0 | 
| T97 | 
110714 | 
651 | 
0 | 
0 | 
| T106 | 
19576 | 
6 | 
0 | 
0 | 
| T111 | 
10594 | 
69 | 
0 | 
0 | 
| T119 | 
37144 | 
253 | 
0 | 
0 | 
| T145 | 
36359 | 
314 | 
0 | 
0 | 
| T146 | 
66867 | 
749 | 
0 | 
0 | 
| T147 | 
30998 | 
102 | 
0 | 
0 | 
| T148 | 
10352 | 
13 | 
0 | 
0 | 
| T149 | 
3796 | 
31 | 
0 | 
0 | 
| T150 | 
13566 | 
28 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5473 | 
0 | 
0 | 
| T97 | 
110714 | 
814 | 
0 | 
0 | 
| T111 | 
10594 | 
63 | 
0 | 
0 | 
| T119 | 
37144 | 
237 | 
0 | 
0 | 
| T145 | 
36359 | 
127 | 
0 | 
0 | 
| T146 | 
66867 | 
544 | 
0 | 
0 | 
| T147 | 
30998 | 
225 | 
0 | 
0 | 
| T148 | 
10352 | 
15 | 
0 | 
0 | 
| T149 | 
3796 | 
5 | 
0 | 
0 | 
| T150 | 
13566 | 
71 | 
0 | 
0 | 
| T151 | 
14200 | 
52 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5352 | 
0 | 
0 | 
| T97 | 
110714 | 
843 | 
0 | 
0 | 
| T111 | 
10594 | 
65 | 
0 | 
0 | 
| T119 | 
37144 | 
260 | 
0 | 
0 | 
| T145 | 
36359 | 
224 | 
0 | 
0 | 
| T146 | 
66867 | 
534 | 
0 | 
0 | 
| T147 | 
30998 | 
169 | 
0 | 
0 | 
| T148 | 
10352 | 
72 | 
0 | 
0 | 
| T149 | 
3796 | 
28 | 
0 | 
0 | 
| T150 | 
13566 | 
15 | 
0 | 
0 | 
| T151 | 
14200 | 
69 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5592 | 
0 | 
0 | 
| T97 | 
110714 | 
732 | 
0 | 
0 | 
| T111 | 
10594 | 
38 | 
0 | 
0 | 
| T119 | 
37144 | 
278 | 
0 | 
0 | 
| T145 | 
36359 | 
304 | 
0 | 
0 | 
| T146 | 
66867 | 
771 | 
0 | 
0 | 
| T147 | 
30998 | 
128 | 
0 | 
0 | 
| T148 | 
10352 | 
57 | 
0 | 
0 | 
| T149 | 
3796 | 
30 | 
0 | 
0 | 
| T150 | 
13566 | 
15 | 
0 | 
0 | 
| T151 | 
14200 | 
113 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4900 | 
0 | 
0 | 
| T97 | 
110714 | 
691 | 
0 | 
0 | 
| T111 | 
10594 | 
71 | 
0 | 
0 | 
| T119 | 
37144 | 
229 | 
0 | 
0 | 
| T145 | 
36359 | 
193 | 
0 | 
0 | 
| T146 | 
66867 | 
645 | 
0 | 
0 | 
| T147 | 
30998 | 
133 | 
0 | 
0 | 
| T148 | 
10352 | 
42 | 
0 | 
0 | 
| T149 | 
3796 | 
5 | 
0 | 
0 | 
| T150 | 
13566 | 
45 | 
0 | 
0 | 
| T151 | 
14200 | 
138 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5056 | 
0 | 
0 | 
| T97 | 
110714 | 
854 | 
0 | 
0 | 
| T111 | 
10594 | 
39 | 
0 | 
0 | 
| T119 | 
37144 | 
199 | 
0 | 
0 | 
| T122 | 
180782 | 
456 | 
0 | 
0 | 
| T145 | 
36359 | 
250 | 
0 | 
0 | 
| T146 | 
66867 | 
641 | 
0 | 
0 | 
| T147 | 
30998 | 
152 | 
0 | 
0 | 
| T148 | 
10352 | 
47 | 
0 | 
0 | 
| T150 | 
13566 | 
41 | 
0 | 
0 | 
| T151 | 
14200 | 
90 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5150 | 
0 | 
0 | 
| T97 | 
110714 | 
621 | 
0 | 
0 | 
| T111 | 
10594 | 
20 | 
0 | 
0 | 
| T119 | 
37144 | 
213 | 
0 | 
0 | 
| T145 | 
36359 | 
269 | 
0 | 
0 | 
| T146 | 
66867 | 
655 | 
0 | 
0 | 
| T147 | 
30998 | 
200 | 
0 | 
0 | 
| T148 | 
10352 | 
139 | 
0 | 
0 | 
| T149 | 
3796 | 
39 | 
0 | 
0 | 
| T150 | 
13566 | 
4 | 
0 | 
0 | 
| T151 | 
14200 | 
8 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5514 | 
0 | 
0 | 
| T97 | 
110714 | 
663 | 
0 | 
0 | 
| T111 | 
10594 | 
29 | 
0 | 
0 | 
| T119 | 
37144 | 
260 | 
0 | 
0 | 
| T145 | 
36359 | 
323 | 
0 | 
0 | 
| T146 | 
66867 | 
620 | 
0 | 
0 | 
| T147 | 
30998 | 
100 | 
0 | 
0 | 
| T148 | 
10352 | 
68 | 
0 | 
0 | 
| T149 | 
3796 | 
5 | 
0 | 
0 | 
| T150 | 
13566 | 
61 | 
0 | 
0 | 
| T151 | 
14200 | 
67 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4924 | 
0 | 
0 | 
| T97 | 
110714 | 
756 | 
0 | 
0 | 
| T111 | 
10594 | 
76 | 
0 | 
0 | 
| T119 | 
37144 | 
201 | 
0 | 
0 | 
| T145 | 
36359 | 
313 | 
0 | 
0 | 
| T146 | 
66867 | 
404 | 
0 | 
0 | 
| T147 | 
30998 | 
147 | 
0 | 
0 | 
| T148 | 
10352 | 
18 | 
0 | 
0 | 
| T149 | 
3796 | 
8 | 
0 | 
0 | 
| T150 | 
13566 | 
28 | 
0 | 
0 | 
| T151 | 
14200 | 
19 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5274 | 
0 | 
0 | 
| T97 | 
110714 | 
904 | 
0 | 
0 | 
| T111 | 
10594 | 
45 | 
0 | 
0 | 
| T119 | 
37144 | 
233 | 
0 | 
0 | 
| T145 | 
36359 | 
246 | 
0 | 
0 | 
| T146 | 
66867 | 
623 | 
0 | 
0 | 
| T147 | 
30998 | 
131 | 
0 | 
0 | 
| T148 | 
10352 | 
91 | 
0 | 
0 | 
| T149 | 
3796 | 
12 | 
0 | 
0 | 
| T150 | 
13566 | 
26 | 
0 | 
0 | 
| T151 | 
14200 | 
148 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5388 | 
0 | 
0 | 
| T97 | 
110714 | 
925 | 
0 | 
0 | 
| T111 | 
10594 | 
30 | 
0 | 
0 | 
| T119 | 
37144 | 
219 | 
0 | 
0 | 
| T145 | 
36359 | 
364 | 
0 | 
0 | 
| T146 | 
66867 | 
480 | 
0 | 
0 | 
| T147 | 
30998 | 
180 | 
0 | 
0 | 
| T148 | 
10352 | 
68 | 
0 | 
0 | 
| T149 | 
3796 | 
21 | 
0 | 
0 | 
| T150 | 
13566 | 
44 | 
0 | 
0 | 
| T151 | 
14200 | 
66 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
5557 | 
0 | 
0 | 
| T97 | 
110714 | 
904 | 
0 | 
0 | 
| T111 | 
10594 | 
20 | 
0 | 
0 | 
| T119 | 
37144 | 
232 | 
0 | 
0 | 
| T122 | 
180782 | 
418 | 
0 | 
0 | 
| T145 | 
36359 | 
397 | 
0 | 
0 | 
| T146 | 
66867 | 
687 | 
0 | 
0 | 
| T147 | 
30998 | 
170 | 
0 | 
0 | 
| T148 | 
10352 | 
15 | 
0 | 
0 | 
| T150 | 
13566 | 
46 | 
0 | 
0 | 
| T151 | 
14200 | 
76 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4910 | 
0 | 
0 | 
| T97 | 
110714 | 
931 | 
0 | 
0 | 
| T111 | 
10594 | 
21 | 
0 | 
0 | 
| T119 | 
37144 | 
248 | 
0 | 
0 | 
| T145 | 
36359 | 
188 | 
0 | 
0 | 
| T146 | 
66867 | 
538 | 
0 | 
0 | 
| T147 | 
30998 | 
137 | 
0 | 
0 | 
| T148 | 
10352 | 
79 | 
0 | 
0 | 
| T149 | 
3796 | 
3 | 
0 | 
0 | 
| T150 | 
13566 | 
32 | 
0 | 
0 | 
| T151 | 
14200 | 
26 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2328 | 
0 | 
0 | 
| T97 | 
110714 | 
176 | 
0 | 
0 | 
| T103 | 
7861 | 
2 | 
0 | 
0 | 
| T111 | 
10594 | 
25 | 
0 | 
0 | 
| T119 | 
37144 | 
238 | 
0 | 
0 | 
| T145 | 
36359 | 
48 | 
0 | 
0 | 
| T146 | 
66867 | 
120 | 
0 | 
0 | 
| T147 | 
30998 | 
21 | 
0 | 
0 | 
| T148 | 
10352 | 
21 | 
0 | 
0 | 
| T149 | 
3796 | 
6 | 
0 | 
0 | 
| T150 | 
13566 | 
47 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2272 | 
0 | 
0 | 
| T97 | 
110714 | 
200 | 
0 | 
0 | 
| T105 | 
15220 | 
2 | 
0 | 
0 | 
| T111 | 
10594 | 
17 | 
0 | 
0 | 
| T119 | 
37144 | 
219 | 
0 | 
0 | 
| T145 | 
36359 | 
59 | 
0 | 
0 | 
| T146 | 
66867 | 
110 | 
0 | 
0 | 
| T147 | 
30998 | 
20 | 
0 | 
0 | 
| T148 | 
10352 | 
15 | 
0 | 
0 | 
| T150 | 
13566 | 
36 | 
0 | 
0 | 
| T151 | 
14200 | 
35 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2408 | 
0 | 
0 | 
| T97 | 
110714 | 
170 | 
0 | 
0 | 
| T111 | 
10594 | 
6 | 
0 | 
0 | 
| T119 | 
37144 | 
243 | 
0 | 
0 | 
| T122 | 
180782 | 
449 | 
0 | 
0 | 
| T145 | 
36359 | 
80 | 
0 | 
0 | 
| T146 | 
66867 | 
118 | 
0 | 
0 | 
| T147 | 
30998 | 
11 | 
0 | 
0 | 
| T148 | 
10352 | 
26 | 
0 | 
0 | 
| T150 | 
13566 | 
53 | 
0 | 
0 | 
| T151 | 
14200 | 
32 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2219 | 
0 | 
0 | 
| T97 | 
110714 | 
155 | 
0 | 
0 | 
| T111 | 
10594 | 
11 | 
0 | 
0 | 
| T119 | 
37144 | 
243 | 
0 | 
0 | 
| T122 | 
180782 | 
455 | 
0 | 
0 | 
| T145 | 
36359 | 
50 | 
0 | 
0 | 
| T146 | 
66867 | 
127 | 
0 | 
0 | 
| T147 | 
30998 | 
17 | 
0 | 
0 | 
| T148 | 
10352 | 
22 | 
0 | 
0 | 
| T150 | 
13566 | 
45 | 
0 | 
0 | 
| T151 | 
14200 | 
23 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2753 | 
0 | 
0 | 
| T97 | 
110714 | 
269 | 
0 | 
0 | 
| T111 | 
10594 | 
6 | 
0 | 
0 | 
| T119 | 
37144 | 
246 | 
0 | 
0 | 
| T145 | 
36359 | 
100 | 
0 | 
0 | 
| T146 | 
66867 | 
174 | 
0 | 
0 | 
| T147 | 
30998 | 
57 | 
0 | 
0 | 
| T148 | 
10352 | 
18 | 
0 | 
0 | 
| T149 | 
3796 | 
4 | 
0 | 
0 | 
| T150 | 
13566 | 
41 | 
0 | 
0 | 
| T151 | 
14200 | 
46 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
4680 | 
0 | 
0 | 
| T20 | 
231256 | 
6 | 
0 | 
0 | 
| T31 | 
0 | 
45 | 
0 | 
0 | 
| T32 | 
0 | 
9 | 
0 | 
0 | 
| T33 | 
0 | 
6 | 
0 | 
0 | 
| T138 | 
96487 | 
0 | 
0 | 
0 | 
| T152 | 
0 | 
12 | 
0 | 
0 | 
| T153 | 
0 | 
30 | 
0 | 
0 | 
| T154 | 
0 | 
9 | 
0 | 
0 | 
| T155 | 
0 | 
9 | 
0 | 
0 | 
| T156 | 
0 | 
33 | 
0 | 
0 | 
| T157 | 
0 | 
31 | 
0 | 
0 | 
| T158 | 
658 | 
0 | 
0 | 
0 | 
| T159 | 
12907 | 
0 | 
0 | 
0 | 
| T160 | 
1691 | 
0 | 
0 | 
0 | 
| T161 | 
167231 | 
0 | 
0 | 
0 | 
| T162 | 
110867 | 
0 | 
0 | 
0 | 
| T163 | 
14962 | 
0 | 
0 | 
0 | 
| T164 | 
1248 | 
0 | 
0 | 
0 | 
| T165 | 
180105 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2307 | 
0 | 
0 | 
| T97 | 
110714 | 
185 | 
0 | 
0 | 
| T111 | 
10594 | 
7 | 
0 | 
0 | 
| T119 | 
37144 | 
237 | 
0 | 
0 | 
| T145 | 
36359 | 
39 | 
0 | 
0 | 
| T146 | 
66867 | 
113 | 
0 | 
0 | 
| T147 | 
30998 | 
45 | 
0 | 
0 | 
| T148 | 
10352 | 
20 | 
0 | 
0 | 
| T149 | 
3796 | 
6 | 
0 | 
0 | 
| T150 | 
13566 | 
65 | 
0 | 
0 | 
| T151 | 
14200 | 
15 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2386 | 
0 | 
0 | 
| T97 | 
110714 | 
204 | 
0 | 
0 | 
| T111 | 
10594 | 
5 | 
0 | 
0 | 
| T119 | 
37144 | 
197 | 
0 | 
0 | 
| T145 | 
36359 | 
53 | 
0 | 
0 | 
| T146 | 
66867 | 
102 | 
0 | 
0 | 
| T147 | 
30998 | 
14 | 
0 | 
0 | 
| T148 | 
10352 | 
18 | 
0 | 
0 | 
| T149 | 
3796 | 
1 | 
0 | 
0 | 
| T150 | 
13566 | 
81 | 
0 | 
0 | 
| T151 | 
14200 | 
52 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2026 | 
0 | 
0 | 
| T97 | 
110714 | 
92 | 
0 | 
0 | 
| T106 | 
19576 | 
6 | 
0 | 
0 | 
| T111 | 
10594 | 
5 | 
0 | 
0 | 
| T119 | 
37144 | 
251 | 
0 | 
0 | 
| T145 | 
36359 | 
27 | 
0 | 
0 | 
| T146 | 
66867 | 
57 | 
0 | 
0 | 
| T147 | 
30998 | 
18 | 
0 | 
0 | 
| T148 | 
10352 | 
16 | 
0 | 
0 | 
| T149 | 
3796 | 
3 | 
0 | 
0 | 
| T150 | 
13566 | 
90 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
1948 | 
0 | 
0 | 
| T97 | 
110714 | 
93 | 
0 | 
0 | 
| T103 | 
7861 | 
1 | 
0 | 
0 | 
| T119 | 
37144 | 
210 | 
0 | 
0 | 
| T145 | 
36359 | 
45 | 
0 | 
0 | 
| T146 | 
66867 | 
74 | 
0 | 
0 | 
| T147 | 
30998 | 
25 | 
0 | 
0 | 
| T148 | 
10352 | 
11 | 
0 | 
0 | 
| T149 | 
3796 | 
7 | 
0 | 
0 | 
| T150 | 
13566 | 
78 | 
0 | 
0 | 
| T151 | 
14200 | 
18 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2036 | 
0 | 
0 | 
| T97 | 
110714 | 
108 | 
0 | 
0 | 
| T111 | 
10594 | 
5 | 
0 | 
0 | 
| T119 | 
37144 | 
219 | 
0 | 
0 | 
| T145 | 
36359 | 
31 | 
0 | 
0 | 
| T146 | 
66867 | 
64 | 
0 | 
0 | 
| T147 | 
30998 | 
6 | 
0 | 
0 | 
| T148 | 
10352 | 
9 | 
0 | 
0 | 
| T149 | 
3796 | 
3 | 
0 | 
0 | 
| T150 | 
13566 | 
31 | 
0 | 
0 | 
| T151 | 
14200 | 
25 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
1990 | 
0 | 
0 | 
| T97 | 
110714 | 
101 | 
0 | 
0 | 
| T111 | 
10594 | 
2 | 
0 | 
0 | 
| T119 | 
37144 | 
259 | 
0 | 
0 | 
| T122 | 
180782 | 
438 | 
0 | 
0 | 
| T145 | 
36359 | 
31 | 
0 | 
0 | 
| T146 | 
66867 | 
83 | 
0 | 
0 | 
| T147 | 
30998 | 
22 | 
0 | 
0 | 
| T148 | 
10352 | 
19 | 
0 | 
0 | 
| T150 | 
13566 | 
23 | 
0 | 
0 | 
| T151 | 
14200 | 
31 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2780 | 
0 | 
0 | 
| T97 | 
110714 | 
227 | 
0 | 
0 | 
| T111 | 
10594 | 
23 | 
0 | 
0 | 
| T119 | 
37144 | 
258 | 
0 | 
0 | 
| T145 | 
36359 | 
66 | 
0 | 
0 | 
| T146 | 
66867 | 
141 | 
0 | 
0 | 
| T147 | 
30998 | 
35 | 
0 | 
0 | 
| T148 | 
10352 | 
15 | 
0 | 
0 | 
| T149 | 
3796 | 
6 | 
0 | 
0 | 
| T150 | 
13566 | 
35 | 
0 | 
0 | 
| T151 | 
14200 | 
40 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2197 | 
0 | 
0 | 
| T97 | 
110714 | 
101 | 
0 | 
0 | 
| T111 | 
10594 | 
7 | 
0 | 
0 | 
| T119 | 
37144 | 
230 | 
0 | 
0 | 
| T145 | 
36359 | 
26 | 
0 | 
0 | 
| T146 | 
66867 | 
74 | 
0 | 
0 | 
| T147 | 
30998 | 
24 | 
0 | 
0 | 
| T148 | 
10352 | 
18 | 
0 | 
0 | 
| T149 | 
3796 | 
7 | 
0 | 
0 | 
| T150 | 
13566 | 
68 | 
0 | 
0 | 
| T151 | 
14200 | 
24 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
3066 | 
0 | 
0 | 
| T97 | 
110714 | 
298 | 
0 | 
0 | 
| T111 | 
10594 | 
25 | 
0 | 
0 | 
| T119 | 
37144 | 
221 | 
0 | 
0 | 
| T145 | 
36359 | 
163 | 
0 | 
0 | 
| T146 | 
66867 | 
192 | 
0 | 
0 | 
| T147 | 
30998 | 
97 | 
0 | 
0 | 
| T148 | 
10352 | 
54 | 
0 | 
0 | 
| T149 | 
3796 | 
7 | 
0 | 
0 | 
| T150 | 
13566 | 
12 | 
0 | 
0 | 
| T151 | 
14200 | 
32 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2199 | 
0 | 
0 | 
| T97 | 
110714 | 
154 | 
0 | 
0 | 
| T111 | 
10594 | 
4 | 
0 | 
0 | 
| T119 | 
37144 | 
246 | 
0 | 
0 | 
| T145 | 
36359 | 
64 | 
0 | 
0 | 
| T146 | 
66867 | 
106 | 
0 | 
0 | 
| T147 | 
30998 | 
36 | 
0 | 
0 | 
| T148 | 
10352 | 
10 | 
0 | 
0 | 
| T149 | 
3796 | 
6 | 
0 | 
0 | 
| T150 | 
13566 | 
50 | 
0 | 
0 | 
| T151 | 
14200 | 
31 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2006 | 
0 | 
0 | 
| T97 | 
110714 | 
149 | 
0 | 
0 | 
| T111 | 
10594 | 
4 | 
0 | 
0 | 
| T119 | 
37144 | 
220 | 
0 | 
0 | 
| T145 | 
36359 | 
35 | 
0 | 
0 | 
| T146 | 
66867 | 
74 | 
0 | 
0 | 
| T147 | 
30998 | 
30 | 
0 | 
0 | 
| T148 | 
10352 | 
6 | 
0 | 
0 | 
| T149 | 
3796 | 
1 | 
0 | 
0 | 
| T150 | 
13566 | 
28 | 
0 | 
0 | 
| T151 | 
14200 | 
14 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2082 | 
0 | 
0 | 
| T97 | 
110714 | 
112 | 
0 | 
0 | 
| T111 | 
10594 | 
7 | 
0 | 
0 | 
| T119 | 
37144 | 
254 | 
0 | 
0 | 
| T145 | 
36359 | 
28 | 
0 | 
0 | 
| T146 | 
66867 | 
66 | 
0 | 
0 | 
| T147 | 
30998 | 
30 | 
0 | 
0 | 
| T148 | 
10352 | 
19 | 
0 | 
0 | 
| T149 | 
3796 | 
2 | 
0 | 
0 | 
| T150 | 
13566 | 
20 | 
0 | 
0 | 
| T151 | 
14200 | 
24 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2027 | 
0 | 
0 | 
| T97 | 
110714 | 
112 | 
0 | 
0 | 
| T119 | 
37144 | 
206 | 
0 | 
0 | 
| T122 | 
180782 | 
444 | 
0 | 
0 | 
| T145 | 
36359 | 
31 | 
0 | 
0 | 
| T146 | 
66867 | 
93 | 
0 | 
0 | 
| T147 | 
30998 | 
30 | 
0 | 
0 | 
| T148 | 
10352 | 
22 | 
0 | 
0 | 
| T149 | 
3796 | 
1 | 
0 | 
0 | 
| T150 | 
13566 | 
43 | 
0 | 
0 | 
| T151 | 
14200 | 
16 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
2188 | 
0 | 
0 | 
| T97 | 
110714 | 
143 | 
0 | 
0 | 
| T111 | 
10594 | 
18 | 
0 | 
0 | 
| T119 | 
37144 | 
255 | 
0 | 
0 | 
| T122 | 
180782 | 
430 | 
0 | 
0 | 
| T145 | 
36359 | 
34 | 
0 | 
0 | 
| T146 | 
66867 | 
72 | 
0 | 
0 | 
| T147 | 
30998 | 
34 | 
0 | 
0 | 
| T148 | 
10352 | 
27 | 
0 | 
0 | 
| T150 | 
13566 | 
43 | 
0 | 
0 | 
| T151 | 
14200 | 
22 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
1969 | 
0 | 
0 | 
| T97 | 
110714 | 
126 | 
0 | 
0 | 
| T111 | 
10594 | 
3 | 
0 | 
0 | 
| T119 | 
37144 | 
192 | 
0 | 
0 | 
| T122 | 
180782 | 
439 | 
0 | 
0 | 
| T145 | 
36359 | 
45 | 
0 | 
0 | 
| T146 | 
66867 | 
94 | 
0 | 
0 | 
| T147 | 
30998 | 
28 | 
0 | 
0 | 
| T148 | 
10352 | 
6 | 
0 | 
0 | 
| T150 | 
13566 | 
32 | 
0 | 
0 | 
| T151 | 
14200 | 
22 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
457312026 | 
1871 | 
0 | 
0 | 
| T97 | 
110714 | 
107 | 
0 | 
0 | 
| T119 | 
37144 | 
192 | 
0 | 
0 | 
| T122 | 
180782 | 
409 | 
0 | 
0 | 
| T145 | 
36359 | 
35 | 
0 | 
0 | 
| T146 | 
66867 | 
64 | 
0 | 
0 | 
| T147 | 
30998 | 
22 | 
0 | 
0 | 
| T148 | 
10352 | 
11 | 
0 | 
0 | 
| T150 | 
13566 | 
53 | 
0 | 
0 | 
| T151 | 
14200 | 
31 | 
0 | 
0 | 
| T166 | 
10934 | 
10 | 
0 | 
0 |