Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3398890	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4223792

1

T1

1386

T2

879

T3

1290

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4138585	1			T1	769		T2	11		T3	768
values[0x0]	1738994	1			T1	430		T2	422		T3	454
values[0x1]	1745103	1			T1	478		T2	456		T3	439

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2417654	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5205028

1

T1

1439

T2

880

T3

1357

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	29822	1			T2	6		T4	2		T9	34
valid_sources[0x01]	29413	1			T2	3		T4	3		T9	31
valid_sources[0x02]	27571	1			T2	3		T4	4		T9	34
valid_sources[0x03]	30613	1			T1	37		T2	8		T4	5
valid_sources[0x04]	28344	1			T2	2		T4	2		T9	37
valid_sources[0x05]	30738	1			T2	4		T4	2		T9	31
valid_sources[0x06]	30349	1			T2	2		T4	3		T9	25
valid_sources[0x07]	34238	1			T2	1		T3	1583		T4	4
valid_sources[0x08]	27090	1			T2	5		T4	8		T9	33
valid_sources[0x09]	28358	1			T2	3		T4	2		T9	29
valid_sources[0x0a]	27427	1			T2	2		T4	4		T9	29
valid_sources[0x0b]	29321	1			T2	2		T4	4		T8	27
valid_sources[0x0c]	34368	1			T2	8		T4	4		T5	166
valid_sources[0x0d]	35704	1			T2	1		T4	4		T5	85
valid_sources[0x0e]	31096	1			T2	2		T4	3		T5	18
valid_sources[0x0f]	28333	1			T2	1		T4	4		T9	26
valid_sources[0x10]	27160	1			T2	7		T4	4		T9	26
valid_sources[0x11]	29431	1			T2	3		T4	2		T9	27
valid_sources[0x12]	27551	1			T2	2		T4	3		T9	25
valid_sources[0x13]	38677	1			T2	5		T4	8		T7	9943
valid_sources[0x14]	26598	1			T2	3		T4	6		T9	32
valid_sources[0x15]	26651	1			T2	3		T4	4		T9	41
valid_sources[0x16]	29378	1			T2	4		T4	8		T6	19
valid_sources[0x17]	27712	1			T4	6		T9	28		T10	30
valid_sources[0x18]	30300	1			T2	3		T4	2		T5	7
valid_sources[0x19]	27708	1			T2	7		T4	7		T5	66
valid_sources[0x1a]	27307	1			T2	5		T4	4		T9	19
valid_sources[0x1b]	27497	1			T2	5		T4	2		T9	21
valid_sources[0x1c]	30323	1			T2	5		T4	2		T9	35
valid_sources[0x1d]	28960	1			T2	3		T4	4		T9	28
valid_sources[0x1e]	26797	1			T2	5		T4	4		T5	42
valid_sources[0x1f]	31533	1			T2	1		T4	7		T9	40
valid_sources[0x20]	28553	1			T2	6		T4	5		T5	28
valid_sources[0x21]	28942	1			T2	4		T4	3		T6	90
valid_sources[0x22]	28796	1			T4	2		T9	27		T10	27
valid_sources[0x23]	30079	1			T2	6		T4	7		T9	20
valid_sources[0x24]	26330	1			T2	5		T4	3		T9	31
valid_sources[0x25]	27580	1			T2	2		T4	3		T9	33
valid_sources[0x26]	31439	1			T2	1		T4	1		T5	102
valid_sources[0x27]	33011	1			T2	6		T4	1		T9	35
valid_sources[0x28]	28223	1			T2	1		T4	1		T5	6
valid_sources[0x29]	29000	1			T2	2		T4	3		T9	38
valid_sources[0x2a]	26756	1			T2	4		T4	6		T9	29
valid_sources[0x2b]	30820	1			T2	9		T9	34		T10	43
valid_sources[0x2c]	28965	1			T2	5		T9	31		T10	38
valid_sources[0x2d]	28208	1			T2	2		T4	6		T9	34
valid_sources[0x2e]	30449	1			T2	1		T4	5		T9	28
valid_sources[0x2f]	28400	1			T2	3		T4	4		T9	34
valid_sources[0x30]	31689	1			T2	6		T4	3		T9	33
valid_sources[0x31]	32096	1			T2	3		T4	4		T9	32
valid_sources[0x32]	30554	1			T2	4		T4	1		T9	39
valid_sources[0x33]	41030	1			T2	8		T4	3		T9	33
valid_sources[0x34]	30179	1			T1	207		T2	4		T4	7
valid_sources[0x35]	26521	1			T2	1		T4	3		T9	30
valid_sources[0x36]	36406	1			T2	1		T4	6		T9	37
valid_sources[0x37]	28121	1			T2	2		T4	3		T9	34
valid_sources[0x38]	29839	1			T2	2		T4	2		T9	32
valid_sources[0x39]	27510	1			T2	2		T4	6		T9	27
valid_sources[0x3a]	29266	1			T2	3		T4	3		T9	27
valid_sources[0x3b]	29265	1			T2	3		T4	5		T9	29
valid_sources[0x3c]	31221	1			T2	1		T4	1		T5	12
valid_sources[0x3d]	28856	1			T4	2		T9	30		T10	24
valid_sources[0x3e]	28586	1			T2	3		T4	1		T9	31
valid_sources[0x3f]	26499	1			T2	1		T9	39		T10	34
valid_sources[0x40]	29789	1			T2	1		T4	4		T5	1
valid_sources[0x41]	29504	1			T2	3		T4	4		T9	22
valid_sources[0x42]	27735	1			T2	2		T4	6		T9	33
valid_sources[0x43]	29882	1			T2	4		T4	5		T9	28
valid_sources[0x44]	34395	1			T2	7		T4	2		T5	26
valid_sources[0x45]	26818	1			T2	2		T4	1		T9	28
valid_sources[0x46]	27531	1			T2	1		T4	5		T9	34
valid_sources[0x47]	32030	1			T2	1		T4	7		T8	10
valid_sources[0x48]	30474	1			T2	2		T4	2		T9	36
valid_sources[0x49]	30957	1			T2	1		T4	2		T9	24
valid_sources[0x4a]	29949	1			T2	6		T4	3		T9	26
valid_sources[0x4b]	25809	1			T2	4		T4	4		T9	36
valid_sources[0x4c]	26216	1			T2	3		T4	6		T6	85
valid_sources[0x4d]	27003	1			T2	2		T4	4		T5	18
valid_sources[0x4e]	26712	1			T2	11		T4	2		T9	28
valid_sources[0x4f]	29024	1			T2	4		T4	3		T5	1
valid_sources[0x50]	31457	1			T2	2		T4	2		T5	10
valid_sources[0x51]	30794	1			T2	3		T4	2		T9	26
valid_sources[0x52]	30537	1			T2	2		T4	4		T5	122
valid_sources[0x53]	26391	1			T2	8		T4	2		T5	23
valid_sources[0x54]	25851	1			T2	3		T4	3		T5	124
valid_sources[0x55]	25843	1			T2	2		T4	1		T5	55
valid_sources[0x56]	29298	1			T2	3		T4	5		T9	27
valid_sources[0x57]	28377	1			T2	1		T3	77		T4	3
valid_sources[0x58]	29915	1			T2	3		T4	4		T5	51
valid_sources[0x59]	28451	1			T2	3		T4	7		T9	37
valid_sources[0x5a]	27277	1			T2	1		T4	11		T6	15
valid_sources[0x5b]	27890	1			T2	3		T4	5		T9	26
valid_sources[0x5c]	30345	1			T2	5		T4	2		T9	35
valid_sources[0x5d]	28192	1			T4	2		T9	27		T10	38
valid_sources[0x5e]	36115	1			T2	5		T4	5		T8	11
valid_sources[0x5f]	26626	1			T2	3		T4	9		T9	28
valid_sources[0x60]	30277	1			T2	2		T4	4		T9	29
valid_sources[0x61]	26649	1			T2	2		T4	7		T5	18
valid_sources[0x62]	28207	1			T4	4		T9	25		T10	30
valid_sources[0x63]	34146	1			T4	1		T9	40		T10	27
valid_sources[0x64]	26675	1			T2	2		T4	2		T9	30
valid_sources[0x65]	28891	1			T2	9		T4	3		T9	32
valid_sources[0x66]	28753	1			T2	1		T4	1		T9	24
valid_sources[0x67]	27128	1			T2	4		T4	2		T9	38
valid_sources[0x68]	29556	1			T2	6		T4	4		T9	41
valid_sources[0x69]	28523	1			T2	1		T4	5		T5	18
valid_sources[0x6a]	30590	1			T2	3		T4	2		T5	84
valid_sources[0x6b]	27763	1			T2	8		T4	1		T9	34
valid_sources[0x6c]	34578	1			T4	8		T5	47		T9	22
valid_sources[0x6d]	30196	1			T2	5		T4	3		T9	26
valid_sources[0x6e]	30170	1			T2	6		T4	4		T9	40
valid_sources[0x6f]	28902	1			T2	9		T4	3		T9	30
valid_sources[0x70]	32755	1			T2	7		T4	1		T5	45
valid_sources[0x71]	32873	1			T2	3		T4	7		T9	20
valid_sources[0x72]	28748	1			T2	5		T4	3		T9	25
valid_sources[0x73]	29234	1			T2	3		T4	7		T5	57
valid_sources[0x74]	28305	1			T2	2		T4	3		T9	26
valid_sources[0x75]	34958	1			T2	4		T4	4		T9	32
valid_sources[0x76]	28556	1			T2	6		T4	1		T9	30
valid_sources[0x77]	27255	1			T2	2		T4	6		T9	30
valid_sources[0x78]	24970	1			T2	3		T4	3		T9	38
valid_sources[0x79]	29232	1			T2	8		T4	2		T9	26
valid_sources[0x7a]	32762	1			T2	6		T4	3		T5	10
valid_sources[0x7b]	28500	1			T2	3		T4	1		T5	51
valid_sources[0x7c]	26823	1			T2	3		T4	2		T9	31
valid_sources[0x7d]	30324	1			T2	3		T4	3		T9	31
valid_sources[0x7e]	29901	1			T2	1		T4	3		T9	45
valid_sources[0x7f]	29551	1			T2	4		T9	31		T10	39
valid_sources[0x80]	31197	1			T2	3		T4	2		T9	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1059555

1

T1

488

T2

3

T3

401

values[0x0]

all_enables

biggest_size

1591819

1

T1

427

T2

421

T3

452

values[0x1]

all_enables

biggest_size

1572418

1

T1

471

T2

455

T3

437