Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3425647

1

T1

291

T2

10

T3

371

full_word

4225330

1

T1

1386

T2

879

T3

1290

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7650587	1			T1	1677		T2	889		T3	1661
auto[TlIntgErrCmd]	143	1			T71	9		T103	5		T104	11
auto[TlIntgErrData]	120	1			T71	15		T103	4		T104	11
auto[TlIntgErrBoth]	127	1			T71	6		T103	11		T104	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4145092

1

T1

769

T2

11

T3

768

auto[1]

3505885

1

T1

908

T2

878

T3

893

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3084889	1			T1	281		T2	8		T3	367
auto[TlIntgErrNone]	partial	auto[1]	340393	1			T1	10		T2	2		T3	4
auto[TlIntgErrNone]	full_word	auto[0]	1060031	1			T1	488		T2	3		T3	401
auto[TlIntgErrNone]	full_word	auto[1]	3165274	1			T1	898		T2	876		T3	889
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T71	5		T103	1		T104	4
auto[TlIntgErrCmd]	partial	auto[1]	75	1			T71	4		T103	3		T104	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T104	1		T185	1		T189	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T103	1		T190	1		T191	1
auto[TlIntgErrData]	partial	auto[0]	56	1			T71	7		T103	1		T104	3
auto[TlIntgErrData]	partial	auto[1]	57	1			T71	7		T103	3		T104	7
auto[TlIntgErrData]	full_word	auto[0]	2	1			T185	1		T190	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T71	1		T104	1		T187	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T71	3		T103	5		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	70	1			T71	2		T103	6		T104	4
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T71	1		T104	1		T185	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T185	1		T192	1		T188	1