Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464055259	2923452	0	0
DepthKnown_A	464055259	463927222	0	0
RvalidKnown_A	464055259	463927222	0	0
WreadyKnown_A	464055259	463927222	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	2923452	0	0
T1	390232	832	0	0
T2	3554	1663	0	0
T3	550093	832	0	0
T4	246775	1663	0	0
T5	119889	1663	0	0
T6	8582	0	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	11642	0	0
T10	181644	3196	0	0
T11	0	1669	0	0
T13	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464055259	3087469	0	0
DepthKnown_A	464055259	463927222	0	0
RvalidKnown_A	464055259	463927222	0	0
WreadyKnown_A	464055259	463927222	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	3087469	0	0
T1	390232	832	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	0	0	0
T7	366197	2496	0	0
T8	1559	0	0	0
T9	213513	6656	0	0
T10	181644	1600	0	0
T11	0	838	0	0
T13	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464055259	200594	0	0
DepthKnown_A	464055259	463927222	0	0
RvalidKnown_A	464055259	463927222	0	0
WreadyKnown_A	464055259	463927222	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	200594	0	0
T1	390232	192	0	0
T2	3554	0	0	0
T3	550093	0	0	0
T4	246775	0	0	0
T5	119889	0	0	0
T6	8582	39	0	0
T7	366197	0	0	0
T8	1559	0	0	0
T9	213513	161	0	0
T10	181644	0	0	0
T12	0	67	0	0
T14	0	1294	0	0
T29	0	1	0	0
T30	0	717	0	0
T31	0	507	0	0
T33	0	27	0	0
T44	0	384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464055259	418478	0	0
DepthKnown_A	464055259	463927222	0	0
RvalidKnown_A	464055259	463927222	0	0
WreadyKnown_A	464055259	463927222	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	418478	0	0
T1	390232	192	0	0
T2	3554	0	0	0
T3	550093	0	0	0
T4	246775	0	0	0
T5	119889	0	0	0
T6	8582	39	0	0
T7	366197	0	0	0
T8	1559	0	0	0
T9	213513	161	0	0
T10	181644	0	0	0
T12	0	67	0	0
T14	0	5614	0	0
T29	0	1	0	0
T30	0	3258	0	0
T31	0	507	0	0
T33	0	27	0	0
T44	0	384	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464055259	5939906	0	0
DepthKnown_A	464055259	463927222	0	0
RvalidKnown_A	464055259	463927222	0	0
WreadyKnown_A	464055259	463927222	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	5939906	0	0
T1	390232	656	0	0
T2	3554	58	0	0
T3	550093	829	0	0
T4	246775	77	0	0
T5	119889	1696	0	0
T6	8582	305	0	0
T7	366197	9111	0	0
T8	1559	51	0	0
T9	213513	1058	0	0
T10	181644	6480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	464055259	11869199	0	0
DepthKnown_A	464055259	463927222	0	0
RvalidKnown_A	464055259	463927222	0	0
WreadyKnown_A	464055259	463927222	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	11869199	0	0
T1	390232	653	0	0
T2	3554	57	0	0
T3	550093	829	0	0
T4	246775	77	0	0
T5	119889	1694	0	0
T6	8582	305	0	0
T7	366197	28542	0	0
T8	1559	51	0	0
T9	213513	1054	0	0
T10	181644	6477	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	464055259	463927222	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0