Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T12,T14
1	0	Unreachable
1	1	Covered	T6,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T14
1	0	Covered	T1,T9,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T9,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	770759461	614650380	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	770759461	3789170	0	0
GntImpliesValid_A	770759461	3789170	0	0
GrantKnown_A	770759461	614650380	0	0
IdxKnown_A	770759461	614650380	0	0
IndexIsCorrect_A	770759461	3789170	0	0
LockArbDecision_A	770759461	0	0	0
NoReadyValidNoGrant_A	770759461	0	0	0
ReadyAndValidImplyGrant_A	770759461	3789170	0	0
ReqAndReadyImplyGrant_A	770759461	3789170	0	0
ReqImpliesValid_A	770759461	3789170	0	0
ReqStaysHighUntilGranted0_M	770759461	0	0	0
RoundRobin_A	770759461	6	0	956
ValidKnown_A	770759461	614650380	0	0
gen_data_port_assertion.DataFlow_A	770759461	3789170	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	614650380	0	0
T1	466164	466097	0	0
T2	3554	3478	0	0
T3	618475	618396	0	0
T4	327129	326766	0	0
T5	269269	269260	0	0
T6	15514	11330	0	0
T7	509045	437535	0	0
T8	1559	1486	0	0
T9	908365	557139	0	0
T10	269364	224968	0	0
T11	371808	185904	0	0
T12	8842	4304	0	0
T13	10464	10368	0	0
T14	969305	960680	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	614650380	0	0
T1	466164	466097	0	0
T2	3554	3478	0	0
T3	618475	618396	0	0
T4	327129	326766	0	0
T5	269269	269260	0	0
T6	15514	11330	0	0
T7	509045	437535	0	0
T8	1559	1486	0	0
T9	908365	557139	0	0
T10	269364	224968	0	0
T11	371808	185904	0	0
T12	8842	4304	0	0
T13	10464	10368	0	0
T14	969305	960680	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	614650380	0	0
T1	466164	466097	0	0
T2	3554	3478	0	0
T3	618475	618396	0	0
T4	327129	326766	0	0
T5	269269	269260	0	0
T6	15514	11330	0	0
T7	509045	437535	0	0
T8	1559	1486	0	0
T9	908365	557139	0	0
T10	269364	224968	0	0
T11	371808	185904	0	0
T12	8842	4304	0	0
T13	10464	10368	0	0
T14	969305	960680	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	6	0	956
T15	213138	0	0	1
T16	380096	0	0	1
T21	0	2	0	0
T23	661922	0	0	1
T24	261517	0	0	1
T25	105053	0	0	1
T26	302640	0	0	1
T27	50811	0	0	1
T59	566964	1	0	1
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	53638	0	0	1
T64	14780	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	614650380	0	0
T1	466164	466097	0	0
T2	3554	3478	0	0
T3	618475	618396	0	0
T4	327129	326766	0	0
T5	269269	269260	0	0
T6	15514	11330	0	0
T7	509045	437535	0	0
T8	1559	1486	0	0
T9	908365	557139	0	0
T10	269364	224968	0	0
T11	371808	185904	0	0
T12	8842	4304	0	0
T13	10464	10368	0	0
T14	969305	960680	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	770759461	3789170	0	0
T1	466164	1816	0	0
T2	3554	832	0	0
T3	618475	832	0	0
T4	327129	832	0	0
T5	269269	832	0	0
T6	15514	248	0	0
T7	509045	832	0	0
T8	1559	0	0	0
T9	908365	7741	0	0
T10	269364	1600	0	0
T11	371808	832	0	0
T12	8842	320	0	0
T13	10464	0	0	0
T14	969305	11921	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	5557	0	0
T33	0	108	0	0
T34	0	2187	0	0
T44	0	3992	0	0
T53	35217	0	0	0
T55	0	2	0	0
T56	0	5442	0	0
T57	0	7147	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T14
1	0	Covered	T6,T12,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T6,T12,T14
1	0	Unreachable
1	1	Covered	T6,T12,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T12,T14
0	0	1	Unreachable
0	0	0	Covered	T6,T12,T14

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T12,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154651276	30143803	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	154651276	661668	0	0
GntImpliesValid_A	154651276	661668	0	0
GrantKnown_A	154651276	30143803	0	0
IdxKnown_A	154651276	30143803	0	0
IndexIsCorrect_A	154651276	661668	0	0
LockArbDecision_A	154651276	0	0	0
NoReadyValidNoGrant_A	154651276	0	0	0
ReadyAndValidImplyGrant_A	154651276	661668	0	0
ReqAndReadyImplyGrant_A	154651276	661668	0	0
ReqImpliesValid_A	154651276	661668	0	0
ReqStaysHighUntilGranted0_M	154651276	0	0	0
RoundRobin_A	154651276	0	0	0
ValidKnown_A	154651276	30143803	0	0
gen_data_port_assertion.DataFlow_A	154651276	661668	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	30143803	0	0
T6	3466	2816	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	4304	0	0
T13	10464	0	0	0
T14	969305	122072	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	30143803	0	0
T6	3466	2816	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	4304	0	0
T13	10464	0	0	0
T14	969305	122072	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	30143803	0	0
T6	3466	2816	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	4304	0	0
T13	10464	0	0	0
T14	969305	122072	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	30143803	0	0
T6	3466	2816	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	4304	0	0
T13	10464	0	0	0
T14	969305	122072	0	0
T28	19143	18408	0	0
T29	0	440	0	0
T30	0	225984	0	0
T31	0	49728	0	0
T32	0	16640	0	0
T33	0	1112	0	0
T34	0	53736	0	0
T53	35217	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	661668	0	0
T6	3466	182	0	0
T7	71424	0	0	0
T9	347426	0	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	320	0	0
T13	10464	0	0	0
T14	969305	4690	0	0
T28	19143	0	0	0
T29	0	12	0	0
T30	0	3850	0	0
T31	0	2036	0	0
T33	0	108	0	0
T34	0	2187	0	0
T53	35217	0	0	0
T56	0	995	0	0
T57	0	1262	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T14

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T9,T14
1	0	Covered	T1,T9,T14

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T1,T9,T14

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T9,T14
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T14
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	154651276	123133257	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	154651276	818439	0	0
GntImpliesValid_A	154651276	818439	0	0
GrantKnown_A	154651276	123133257	0	0
IdxKnown_A	154651276	123133257	0	0
IndexIsCorrect_A	154651276	818439	0	0
LockArbDecision_A	154651276	0	0	0
NoReadyValidNoGrant_A	154651276	0	0	0
ReadyAndValidImplyGrant_A	154651276	818439	0	0
ReqAndReadyImplyGrant_A	154651276	818439	0	0
ReqImpliesValid_A	154651276	818439	0	0
ReqStaysHighUntilGranted0_M	154651276	0	0	0
RoundRobin_A	154651276	0	0	0
ValidKnown_A	154651276	123133257	0	0
gen_data_port_assertion.DataFlow_A	154651276	818439	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	123133257	0	0
T1	75932	75932	0	0
T3	68382	68382	0	0
T4	80354	80076	0	0
T5	149380	149380	0	0
T6	3466	0	0	0
T7	71424	71424	0	0
T9	347426	343710	0	0
T10	43860	43376	0	0
T11	185904	185904	0	0
T12	4421	0	0	0
T13	0	10368	0	0
T14	0	838608	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	123133257	0	0
T1	75932	75932	0	0
T3	68382	68382	0	0
T4	80354	80076	0	0
T5	149380	149380	0	0
T6	3466	0	0	0
T7	71424	71424	0	0
T9	347426	343710	0	0
T10	43860	43376	0	0
T11	185904	185904	0	0
T12	4421	0	0	0
T13	0	10368	0	0
T14	0	838608	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	123133257	0	0
T1	75932	75932	0	0
T3	68382	68382	0	0
T4	80354	80076	0	0
T5	149380	149380	0	0
T6	3466	0	0	0
T7	71424	71424	0	0
T9	347426	343710	0	0
T10	43860	43376	0	0
T11	185904	185904	0	0
T12	4421	0	0	0
T13	0	10368	0	0
T14	0	838608	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	123133257	0	0
T1	75932	75932	0	0
T3	68382	68382	0	0
T4	80354	80076	0	0
T5	149380	149380	0	0
T6	3466	0	0	0
T7	71424	71424	0	0
T9	347426	343710	0	0
T10	43860	43376	0	0
T11	185904	185904	0	0
T12	4421	0	0	0
T13	0	10368	0	0
T14	0	838608	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	154651276	818439	0	0
T1	75932	780	0	0
T3	68382	0	0	0
T4	80354	0	0	0
T5	149380	0	0	0
T6	3466	0	0	0
T7	71424	0	0	0
T9	347426	914	0	0
T10	43860	0	0	0
T11	185904	0	0	0
T12	4421	0	0	0
T14	0	7231	0	0
T31	0	3521	0	0
T43	0	9908	0	0
T44	0	3992	0	0
T51	0	7	0	0
T55	0	2	0	0
T56	0	4447	0	0
T57	0	5885	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T6,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T9
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	461456909	461373320	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	461456909	2309063	0	0
GntImpliesValid_A	461456909	2309063	0	0
GrantKnown_A	461456909	461373320	0	0
IdxKnown_A	461456909	461373320	0	0
IndexIsCorrect_A	461456909	2309063	0	0
LockArbDecision_A	461456909	0	0	0
NoReadyValidNoGrant_A	461456909	0	0	0
ReadyAndValidImplyGrant_A	461456909	2309063	0	0
ReqAndReadyImplyGrant_A	461456909	2309063	0	0
ReqImpliesValid_A	461456909	2309063	0	0
ReqStaysHighUntilGranted0_M	461456909	0	0	0
RoundRobin_A	461456909	6	0	956
ValidKnown_A	461456909	461373320	0	0
gen_data_port_assertion.DataFlow_A	461456909	2309063	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	461373320	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	461373320	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	461373320	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	6	0	956
T15	213138	0	0	1
T16	380096	0	0	1
T21	0	2	0	0
T23	661922	0	0	1
T24	261517	0	0	1
T25	105053	0	0	1
T26	302640	0	0	1
T27	50811	0	0	1
T59	566964	1	0	1
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	53638	0	0	1
T64	14780	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	461373320	0	0
T1	390232	390165	0	0
T2	3554	3478	0	0
T3	550093	550014	0	0
T4	246775	246690	0	0
T5	119889	119880	0	0
T6	8582	8514	0	0
T7	366197	366111	0	0
T8	1559	1486	0	0
T9	213513	213429	0	0
T10	181644	181592	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	461456909	2309063	0	0
T1	390232	1036	0	0
T2	3554	832	0	0
T3	550093	832	0	0
T4	246775	832	0	0
T5	119889	832	0	0
T6	8582	66	0	0
T7	366197	832	0	0
T8	1559	0	0	0
T9	213513	6827	0	0
T10	181644	1600	0	0
T11	0	832	0	0