Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
3622 |
0 |
0 |
T70 |
10810 |
145 |
0 |
0 |
T71 |
102097 |
7 |
0 |
0 |
T72 |
2042 |
6 |
0 |
0 |
T102 |
4710 |
11 |
0 |
0 |
T105 |
20759 |
210 |
0 |
0 |
T106 |
8831 |
5 |
0 |
0 |
T109 |
8615 |
44 |
0 |
0 |
T114 |
9094 |
3 |
0 |
0 |
T118 |
11557 |
10 |
0 |
0 |
T120 |
14077 |
7 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2515 |
0 |
0 |
T71 |
102097 |
140 |
0 |
0 |
T89 |
5010 |
9 |
0 |
0 |
T90 |
4135 |
4 |
0 |
0 |
T104 |
101678 |
104 |
0 |
0 |
T120 |
14077 |
7 |
0 |
0 |
T127 |
270598 |
634 |
0 |
0 |
T128 |
269094 |
680 |
0 |
0 |
T162 |
7286 |
5 |
0 |
0 |
T163 |
11945 |
33 |
0 |
0 |
T164 |
20806 |
93 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2312 |
0 |
0 |
T71 |
102097 |
127 |
0 |
0 |
T89 |
5010 |
3 |
0 |
0 |
T90 |
4135 |
6 |
0 |
0 |
T104 |
101678 |
142 |
0 |
0 |
T120 |
14077 |
3 |
0 |
0 |
T127 |
270598 |
653 |
0 |
0 |
T128 |
269094 |
584 |
0 |
0 |
T163 |
11945 |
7 |
0 |
0 |
T164 |
20806 |
38 |
0 |
0 |
T165 |
7204 |
37 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
3252 |
0 |
0 |
T71 |
102097 |
290 |
0 |
0 |
T89 |
5010 |
19 |
0 |
0 |
T90 |
4135 |
5 |
0 |
0 |
T104 |
101678 |
235 |
0 |
0 |
T120 |
14077 |
41 |
0 |
0 |
T127 |
270598 |
687 |
0 |
0 |
T128 |
269094 |
678 |
0 |
0 |
T162 |
7286 |
6 |
0 |
0 |
T163 |
11945 |
23 |
0 |
0 |
T164 |
20806 |
89 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
13191 |
0 |
0 |
T71 |
102097 |
2064 |
0 |
0 |
T89 |
5010 |
8 |
0 |
0 |
T90 |
4135 |
7 |
0 |
0 |
T104 |
101678 |
2136 |
0 |
0 |
T120 |
14077 |
70 |
0 |
0 |
T127 |
270598 |
710 |
0 |
0 |
T128 |
269094 |
674 |
0 |
0 |
T162 |
7286 |
136 |
0 |
0 |
T163 |
11945 |
36 |
0 |
0 |
T164 |
20806 |
68 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
12160 |
0 |
0 |
T71 |
102097 |
2051 |
0 |
0 |
T89 |
5010 |
16 |
0 |
0 |
T90 |
4135 |
2 |
0 |
0 |
T104 |
101678 |
1858 |
0 |
0 |
T120 |
14077 |
40 |
0 |
0 |
T127 |
270598 |
673 |
0 |
0 |
T128 |
269094 |
672 |
0 |
0 |
T162 |
7286 |
103 |
0 |
0 |
T163 |
11945 |
25 |
0 |
0 |
T164 |
20806 |
76 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
11682 |
0 |
0 |
T71 |
102097 |
2347 |
0 |
0 |
T89 |
5010 |
9 |
0 |
0 |
T90 |
4135 |
15 |
0 |
0 |
T104 |
101678 |
2064 |
0 |
0 |
T120 |
14077 |
139 |
0 |
0 |
T127 |
270598 |
711 |
0 |
0 |
T128 |
269094 |
624 |
0 |
0 |
T162 |
7286 |
9 |
0 |
0 |
T163 |
11945 |
18 |
0 |
0 |
T164 |
20806 |
28 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
13002 |
0 |
0 |
T71 |
102097 |
2005 |
0 |
0 |
T89 |
5010 |
14 |
0 |
0 |
T90 |
4135 |
2 |
0 |
0 |
T104 |
101678 |
2346 |
0 |
0 |
T120 |
14077 |
70 |
0 |
0 |
T127 |
270598 |
717 |
0 |
0 |
T128 |
269094 |
657 |
0 |
0 |
T162 |
7286 |
95 |
0 |
0 |
T164 |
20806 |
77 |
0 |
0 |
T165 |
7204 |
29 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
11612 |
0 |
0 |
T71 |
102097 |
2041 |
0 |
0 |
T89 |
5010 |
8 |
0 |
0 |
T90 |
4135 |
19 |
0 |
0 |
T104 |
101678 |
1656 |
0 |
0 |
T120 |
14077 |
52 |
0 |
0 |
T127 |
270598 |
706 |
0 |
0 |
T128 |
269094 |
689 |
0 |
0 |
T162 |
7286 |
89 |
0 |
0 |
T163 |
11945 |
4 |
0 |
0 |
T164 |
20806 |
77 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
11936 |
0 |
0 |
T71 |
102097 |
1987 |
0 |
0 |
T89 |
5010 |
13 |
0 |
0 |
T90 |
4135 |
18 |
0 |
0 |
T104 |
101678 |
2071 |
0 |
0 |
T120 |
14077 |
163 |
0 |
0 |
T127 |
270598 |
643 |
0 |
0 |
T128 |
269094 |
687 |
0 |
0 |
T162 |
7286 |
63 |
0 |
0 |
T163 |
11945 |
48 |
0 |
0 |
T164 |
20806 |
54 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
11918 |
0 |
0 |
T71 |
102097 |
1633 |
0 |
0 |
T89 |
5010 |
9 |
0 |
0 |
T90 |
4135 |
11 |
0 |
0 |
T104 |
101678 |
1730 |
0 |
0 |
T120 |
14077 |
150 |
0 |
0 |
T127 |
270598 |
643 |
0 |
0 |
T128 |
269094 |
676 |
0 |
0 |
T162 |
7286 |
58 |
0 |
0 |
T163 |
11945 |
59 |
0 |
0 |
T164 |
20806 |
97 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
11717 |
0 |
0 |
T71 |
102097 |
2003 |
0 |
0 |
T89 |
5010 |
10 |
0 |
0 |
T90 |
4135 |
9 |
0 |
0 |
T104 |
101678 |
1922 |
0 |
0 |
T120 |
14077 |
170 |
0 |
0 |
T127 |
270598 |
644 |
0 |
0 |
T128 |
269094 |
640 |
0 |
0 |
T162 |
7286 |
90 |
0 |
0 |
T163 |
11945 |
13 |
0 |
0 |
T164 |
20806 |
91 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6585 |
0 |
0 |
T71 |
102097 |
925 |
0 |
0 |
T89 |
5010 |
18 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
783 |
0 |
0 |
T120 |
14077 |
39 |
0 |
0 |
T127 |
270598 |
641 |
0 |
0 |
T128 |
269094 |
727 |
0 |
0 |
T162 |
7286 |
17 |
0 |
0 |
T163 |
11945 |
18 |
0 |
0 |
T164 |
20806 |
85 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5822 |
0 |
0 |
T71 |
102097 |
859 |
0 |
0 |
T89 |
5010 |
8 |
0 |
0 |
T90 |
4135 |
7 |
0 |
0 |
T104 |
101678 |
706 |
0 |
0 |
T120 |
14077 |
56 |
0 |
0 |
T127 |
270598 |
645 |
0 |
0 |
T128 |
269094 |
627 |
0 |
0 |
T162 |
7286 |
21 |
0 |
0 |
T163 |
11945 |
24 |
0 |
0 |
T164 |
20806 |
60 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6247 |
0 |
0 |
T71 |
102097 |
767 |
0 |
0 |
T89 |
5010 |
7 |
0 |
0 |
T90 |
4135 |
3 |
0 |
0 |
T104 |
101678 |
739 |
0 |
0 |
T120 |
14077 |
51 |
0 |
0 |
T127 |
270598 |
660 |
0 |
0 |
T128 |
269094 |
671 |
0 |
0 |
T162 |
7286 |
5 |
0 |
0 |
T163 |
11945 |
6 |
0 |
0 |
T164 |
20806 |
61 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5972 |
0 |
0 |
T71 |
102097 |
788 |
0 |
0 |
T89 |
5010 |
16 |
0 |
0 |
T90 |
4135 |
4 |
0 |
0 |
T104 |
101678 |
704 |
0 |
0 |
T120 |
14077 |
89 |
0 |
0 |
T127 |
270598 |
695 |
0 |
0 |
T128 |
269094 |
714 |
0 |
0 |
T162 |
7286 |
24 |
0 |
0 |
T163 |
11945 |
13 |
0 |
0 |
T164 |
20806 |
84 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6772 |
0 |
0 |
T71 |
102097 |
982 |
0 |
0 |
T89 |
5010 |
11 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
523 |
0 |
0 |
T120 |
14077 |
93 |
0 |
0 |
T127 |
270598 |
696 |
0 |
0 |
T128 |
269094 |
716 |
0 |
0 |
T162 |
7286 |
6 |
0 |
0 |
T163 |
11945 |
42 |
0 |
0 |
T164 |
20806 |
54 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6515 |
0 |
0 |
T71 |
102097 |
1015 |
0 |
0 |
T89 |
5010 |
12 |
0 |
0 |
T90 |
4135 |
6 |
0 |
0 |
T104 |
101678 |
823 |
0 |
0 |
T120 |
14077 |
49 |
0 |
0 |
T127 |
270598 |
669 |
0 |
0 |
T128 |
269094 |
674 |
0 |
0 |
T162 |
7286 |
11 |
0 |
0 |
T163 |
11945 |
26 |
0 |
0 |
T164 |
20806 |
81 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5988 |
0 |
0 |
T71 |
102097 |
742 |
0 |
0 |
T89 |
5010 |
11 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
769 |
0 |
0 |
T120 |
14077 |
93 |
0 |
0 |
T127 |
270598 |
654 |
0 |
0 |
T128 |
269094 |
654 |
0 |
0 |
T162 |
7286 |
63 |
0 |
0 |
T163 |
11945 |
2 |
0 |
0 |
T164 |
20806 |
84 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5974 |
0 |
0 |
T71 |
102097 |
755 |
0 |
0 |
T89 |
5010 |
17 |
0 |
0 |
T90 |
4135 |
14 |
0 |
0 |
T104 |
101678 |
658 |
0 |
0 |
T120 |
14077 |
16 |
0 |
0 |
T127 |
270598 |
707 |
0 |
0 |
T128 |
269094 |
646 |
0 |
0 |
T162 |
7286 |
3 |
0 |
0 |
T163 |
11945 |
4 |
0 |
0 |
T164 |
20806 |
78 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6235 |
0 |
0 |
T71 |
102097 |
920 |
0 |
0 |
T89 |
5010 |
11 |
0 |
0 |
T90 |
4135 |
2 |
0 |
0 |
T104 |
101678 |
775 |
0 |
0 |
T120 |
14077 |
29 |
0 |
0 |
T127 |
270598 |
626 |
0 |
0 |
T128 |
269094 |
661 |
0 |
0 |
T162 |
7286 |
25 |
0 |
0 |
T163 |
11945 |
33 |
0 |
0 |
T164 |
20806 |
43 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6004 |
0 |
0 |
T71 |
102097 |
614 |
0 |
0 |
T89 |
5010 |
12 |
0 |
0 |
T90 |
4135 |
6 |
0 |
0 |
T104 |
101678 |
982 |
0 |
0 |
T120 |
14077 |
43 |
0 |
0 |
T127 |
270598 |
696 |
0 |
0 |
T128 |
269094 |
702 |
0 |
0 |
T162 |
7286 |
36 |
0 |
0 |
T163 |
11945 |
30 |
0 |
0 |
T164 |
20806 |
84 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5931 |
0 |
0 |
T71 |
102097 |
861 |
0 |
0 |
T89 |
5010 |
4 |
0 |
0 |
T90 |
4135 |
10 |
0 |
0 |
T104 |
101678 |
577 |
0 |
0 |
T120 |
14077 |
41 |
0 |
0 |
T127 |
270598 |
724 |
0 |
0 |
T128 |
269094 |
636 |
0 |
0 |
T162 |
7286 |
35 |
0 |
0 |
T163 |
11945 |
34 |
0 |
0 |
T164 |
20806 |
117 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
7012 |
0 |
0 |
T71 |
102097 |
844 |
0 |
0 |
T89 |
5010 |
19 |
0 |
0 |
T90 |
4135 |
5 |
0 |
0 |
T104 |
101678 |
1006 |
0 |
0 |
T120 |
14077 |
45 |
0 |
0 |
T127 |
270598 |
604 |
0 |
0 |
T128 |
269094 |
716 |
0 |
0 |
T162 |
7286 |
35 |
0 |
0 |
T163 |
11945 |
13 |
0 |
0 |
T164 |
20806 |
66 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6230 |
0 |
0 |
T71 |
102097 |
773 |
0 |
0 |
T89 |
5010 |
5 |
0 |
0 |
T90 |
4135 |
7 |
0 |
0 |
T104 |
101678 |
795 |
0 |
0 |
T120 |
14077 |
65 |
0 |
0 |
T127 |
270598 |
741 |
0 |
0 |
T128 |
269094 |
660 |
0 |
0 |
T162 |
7286 |
42 |
0 |
0 |
T163 |
11945 |
37 |
0 |
0 |
T164 |
20806 |
37 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6083 |
0 |
0 |
T71 |
102097 |
660 |
0 |
0 |
T89 |
5010 |
12 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
866 |
0 |
0 |
T120 |
14077 |
42 |
0 |
0 |
T127 |
270598 |
605 |
0 |
0 |
T128 |
269094 |
641 |
0 |
0 |
T162 |
7286 |
28 |
0 |
0 |
T163 |
11945 |
15 |
0 |
0 |
T164 |
20806 |
75 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6289 |
0 |
0 |
T71 |
102097 |
911 |
0 |
0 |
T89 |
5010 |
17 |
0 |
0 |
T90 |
4135 |
15 |
0 |
0 |
T104 |
101678 |
1007 |
0 |
0 |
T120 |
14077 |
23 |
0 |
0 |
T127 |
270598 |
636 |
0 |
0 |
T128 |
269094 |
662 |
0 |
0 |
T162 |
7286 |
52 |
0 |
0 |
T163 |
11945 |
29 |
0 |
0 |
T164 |
20806 |
46 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5833 |
0 |
0 |
T71 |
102097 |
902 |
0 |
0 |
T89 |
5010 |
14 |
0 |
0 |
T90 |
4135 |
11 |
0 |
0 |
T104 |
101678 |
941 |
0 |
0 |
T120 |
14077 |
67 |
0 |
0 |
T127 |
270598 |
666 |
0 |
0 |
T128 |
269094 |
714 |
0 |
0 |
T162 |
7286 |
15 |
0 |
0 |
T163 |
11945 |
24 |
0 |
0 |
T164 |
20806 |
66 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5971 |
0 |
0 |
T71 |
102097 |
573 |
0 |
0 |
T89 |
5010 |
22 |
0 |
0 |
T90 |
4135 |
10 |
0 |
0 |
T104 |
101678 |
539 |
0 |
0 |
T120 |
14077 |
52 |
0 |
0 |
T127 |
270598 |
610 |
0 |
0 |
T128 |
269094 |
672 |
0 |
0 |
T162 |
7286 |
22 |
0 |
0 |
T163 |
11945 |
22 |
0 |
0 |
T164 |
20806 |
88 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5899 |
0 |
0 |
T71 |
102097 |
666 |
0 |
0 |
T89 |
5010 |
26 |
0 |
0 |
T90 |
4135 |
21 |
0 |
0 |
T104 |
101678 |
797 |
0 |
0 |
T120 |
14077 |
31 |
0 |
0 |
T127 |
270598 |
656 |
0 |
0 |
T128 |
269094 |
686 |
0 |
0 |
T162 |
7286 |
13 |
0 |
0 |
T163 |
11945 |
13 |
0 |
0 |
T164 |
20806 |
28 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6191 |
0 |
0 |
T71 |
102097 |
969 |
0 |
0 |
T89 |
5010 |
16 |
0 |
0 |
T90 |
4135 |
16 |
0 |
0 |
T104 |
101678 |
856 |
0 |
0 |
T120 |
14077 |
43 |
0 |
0 |
T127 |
270598 |
694 |
0 |
0 |
T128 |
269094 |
748 |
0 |
0 |
T162 |
7286 |
28 |
0 |
0 |
T163 |
11945 |
6 |
0 |
0 |
T164 |
20806 |
108 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6255 |
0 |
0 |
T71 |
102097 |
851 |
0 |
0 |
T89 |
5010 |
13 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
970 |
0 |
0 |
T120 |
14077 |
17 |
0 |
0 |
T127 |
270598 |
746 |
0 |
0 |
T128 |
269094 |
645 |
0 |
0 |
T162 |
7286 |
2 |
0 |
0 |
T163 |
11945 |
4 |
0 |
0 |
T164 |
20806 |
64 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6284 |
0 |
0 |
T71 |
102097 |
788 |
0 |
0 |
T89 |
5010 |
10 |
0 |
0 |
T90 |
4135 |
13 |
0 |
0 |
T104 |
101678 |
935 |
0 |
0 |
T120 |
14077 |
86 |
0 |
0 |
T127 |
270598 |
662 |
0 |
0 |
T128 |
269094 |
672 |
0 |
0 |
T162 |
7286 |
4 |
0 |
0 |
T163 |
11945 |
27 |
0 |
0 |
T164 |
20806 |
64 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5931 |
0 |
0 |
T71 |
102097 |
682 |
0 |
0 |
T89 |
5010 |
4 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
949 |
0 |
0 |
T120 |
14077 |
53 |
0 |
0 |
T127 |
270598 |
670 |
0 |
0 |
T128 |
269094 |
641 |
0 |
0 |
T162 |
7286 |
33 |
0 |
0 |
T163 |
11945 |
38 |
0 |
0 |
T164 |
20806 |
85 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6369 |
0 |
0 |
T71 |
102097 |
844 |
0 |
0 |
T89 |
5010 |
7 |
0 |
0 |
T90 |
4135 |
4 |
0 |
0 |
T104 |
101678 |
797 |
0 |
0 |
T120 |
14077 |
51 |
0 |
0 |
T127 |
270598 |
703 |
0 |
0 |
T128 |
269094 |
710 |
0 |
0 |
T162 |
7286 |
44 |
0 |
0 |
T163 |
11945 |
13 |
0 |
0 |
T164 |
20806 |
77 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
6339 |
0 |
0 |
T71 |
102097 |
786 |
0 |
0 |
T89 |
5010 |
15 |
0 |
0 |
T90 |
4135 |
26 |
0 |
0 |
T104 |
101678 |
786 |
0 |
0 |
T120 |
14077 |
62 |
0 |
0 |
T127 |
270598 |
734 |
0 |
0 |
T128 |
269094 |
626 |
0 |
0 |
T162 |
7286 |
41 |
0 |
0 |
T163 |
11945 |
7 |
0 |
0 |
T164 |
20806 |
78 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2639 |
0 |
0 |
T71 |
102097 |
163 |
0 |
0 |
T89 |
5010 |
4 |
0 |
0 |
T90 |
4135 |
10 |
0 |
0 |
T104 |
101678 |
164 |
0 |
0 |
T120 |
14077 |
21 |
0 |
0 |
T127 |
270598 |
659 |
0 |
0 |
T128 |
269094 |
651 |
0 |
0 |
T162 |
7286 |
3 |
0 |
0 |
T163 |
11945 |
28 |
0 |
0 |
T164 |
20806 |
22 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2796 |
0 |
0 |
T71 |
102097 |
153 |
0 |
0 |
T89 |
5010 |
8 |
0 |
0 |
T90 |
4135 |
14 |
0 |
0 |
T104 |
101678 |
158 |
0 |
0 |
T120 |
14077 |
14 |
0 |
0 |
T127 |
270598 |
691 |
0 |
0 |
T128 |
269094 |
723 |
0 |
0 |
T162 |
7286 |
5 |
0 |
0 |
T163 |
11945 |
26 |
0 |
0 |
T164 |
20806 |
61 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2799 |
0 |
0 |
T71 |
102097 |
159 |
0 |
0 |
T89 |
5010 |
4 |
0 |
0 |
T90 |
4135 |
3 |
0 |
0 |
T104 |
101678 |
183 |
0 |
0 |
T120 |
14077 |
4 |
0 |
0 |
T127 |
270598 |
695 |
0 |
0 |
T128 |
269094 |
669 |
0 |
0 |
T162 |
7286 |
10 |
0 |
0 |
T163 |
11945 |
49 |
0 |
0 |
T164 |
20806 |
50 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2834 |
0 |
0 |
T71 |
102097 |
203 |
0 |
0 |
T89 |
5010 |
16 |
0 |
0 |
T90 |
4135 |
8 |
0 |
0 |
T104 |
101678 |
166 |
0 |
0 |
T109 |
8615 |
1 |
0 |
0 |
T120 |
14077 |
21 |
0 |
0 |
T127 |
270598 |
715 |
0 |
0 |
T128 |
269094 |
640 |
0 |
0 |
T162 |
7286 |
10 |
0 |
0 |
T163 |
11945 |
30 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
3611 |
0 |
0 |
T71 |
102097 |
368 |
0 |
0 |
T89 |
5010 |
11 |
0 |
0 |
T90 |
4135 |
11 |
0 |
0 |
T104 |
101678 |
344 |
0 |
0 |
T120 |
14077 |
33 |
0 |
0 |
T127 |
270598 |
682 |
0 |
0 |
T128 |
269094 |
632 |
0 |
0 |
T162 |
7286 |
18 |
0 |
0 |
T163 |
11945 |
46 |
0 |
0 |
T164 |
20806 |
60 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
5498 |
0 |
0 |
T18 |
363349 |
84 |
0 |
0 |
T36 |
0 |
48 |
0 |
0 |
T149 |
0 |
24 |
0 |
0 |
T161 |
111062 |
0 |
0 |
0 |
T166 |
0 |
17 |
0 |
0 |
T167 |
0 |
85 |
0 |
0 |
T168 |
0 |
17 |
0 |
0 |
T169 |
0 |
56 |
0 |
0 |
T170 |
0 |
33 |
0 |
0 |
T171 |
0 |
34 |
0 |
0 |
T172 |
0 |
8 |
0 |
0 |
T173 |
113895 |
0 |
0 |
0 |
T174 |
91393 |
0 |
0 |
0 |
T175 |
5783 |
0 |
0 |
0 |
T176 |
72043 |
0 |
0 |
0 |
T177 |
317133 |
0 |
0 |
0 |
T178 |
989 |
0 |
0 |
0 |
T179 |
96593 |
0 |
0 |
0 |
T180 |
20531 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2771 |
0 |
0 |
T71 |
102097 |
175 |
0 |
0 |
T89 |
5010 |
6 |
0 |
0 |
T90 |
4135 |
8 |
0 |
0 |
T104 |
101678 |
176 |
0 |
0 |
T120 |
14077 |
15 |
0 |
0 |
T127 |
270598 |
734 |
0 |
0 |
T128 |
269094 |
654 |
0 |
0 |
T162 |
7286 |
8 |
0 |
0 |
T163 |
11945 |
7 |
0 |
0 |
T164 |
20806 |
67 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2832 |
0 |
0 |
T71 |
102097 |
179 |
0 |
0 |
T89 |
5010 |
8 |
0 |
0 |
T90 |
4135 |
7 |
0 |
0 |
T104 |
101678 |
178 |
0 |
0 |
T120 |
14077 |
14 |
0 |
0 |
T127 |
270598 |
687 |
0 |
0 |
T128 |
269094 |
581 |
0 |
0 |
T162 |
7286 |
2 |
0 |
0 |
T163 |
11945 |
53 |
0 |
0 |
T164 |
20806 |
71 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2466 |
0 |
0 |
T71 |
102097 |
89 |
0 |
0 |
T89 |
5010 |
4 |
0 |
0 |
T90 |
4135 |
10 |
0 |
0 |
T104 |
101678 |
124 |
0 |
0 |
T120 |
14077 |
16 |
0 |
0 |
T127 |
270598 |
621 |
0 |
0 |
T128 |
269094 |
706 |
0 |
0 |
T162 |
7286 |
1 |
0 |
0 |
T163 |
11945 |
60 |
0 |
0 |
T164 |
20806 |
54 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2478 |
0 |
0 |
T71 |
102097 |
145 |
0 |
0 |
T89 |
5010 |
6 |
0 |
0 |
T90 |
4135 |
1 |
0 |
0 |
T104 |
101678 |
123 |
0 |
0 |
T120 |
14077 |
18 |
0 |
0 |
T127 |
270598 |
661 |
0 |
0 |
T128 |
269094 |
676 |
0 |
0 |
T163 |
11945 |
46 |
0 |
0 |
T164 |
20806 |
43 |
0 |
0 |
T165 |
7204 |
5 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2473 |
0 |
0 |
T71 |
102097 |
138 |
0 |
0 |
T89 |
5010 |
13 |
0 |
0 |
T90 |
4135 |
4 |
0 |
0 |
T104 |
101678 |
136 |
0 |
0 |
T120 |
14077 |
15 |
0 |
0 |
T127 |
270598 |
672 |
0 |
0 |
T128 |
269094 |
657 |
0 |
0 |
T162 |
7286 |
1 |
0 |
0 |
T163 |
11945 |
10 |
0 |
0 |
T164 |
20806 |
90 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2550 |
0 |
0 |
T71 |
102097 |
89 |
0 |
0 |
T89 |
5010 |
15 |
0 |
0 |
T90 |
4135 |
7 |
0 |
0 |
T104 |
101678 |
126 |
0 |
0 |
T120 |
14077 |
2 |
0 |
0 |
T127 |
270598 |
680 |
0 |
0 |
T128 |
269094 |
656 |
0 |
0 |
T162 |
7286 |
9 |
0 |
0 |
T163 |
11945 |
2 |
0 |
0 |
T164 |
20806 |
36 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
3385 |
0 |
0 |
T71 |
102097 |
205 |
0 |
0 |
T89 |
5010 |
5 |
0 |
0 |
T90 |
4135 |
1 |
0 |
0 |
T104 |
101678 |
293 |
0 |
0 |
T120 |
14077 |
6 |
0 |
0 |
T127 |
270598 |
671 |
0 |
0 |
T128 |
269094 |
676 |
0 |
0 |
T162 |
7286 |
6 |
0 |
0 |
T163 |
11945 |
26 |
0 |
0 |
T164 |
20806 |
115 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2365 |
0 |
0 |
T71 |
102097 |
113 |
0 |
0 |
T89 |
5010 |
13 |
0 |
0 |
T90 |
4135 |
8 |
0 |
0 |
T104 |
101678 |
106 |
0 |
0 |
T120 |
14077 |
18 |
0 |
0 |
T127 |
270598 |
567 |
0 |
0 |
T128 |
269094 |
647 |
0 |
0 |
T162 |
7286 |
4 |
0 |
0 |
T164 |
20806 |
72 |
0 |
0 |
T165 |
7204 |
44 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
3509 |
0 |
0 |
T71 |
102097 |
281 |
0 |
0 |
T89 |
5010 |
15 |
0 |
0 |
T90 |
4135 |
16 |
0 |
0 |
T104 |
101678 |
283 |
0 |
0 |
T120 |
14077 |
43 |
0 |
0 |
T127 |
270598 |
658 |
0 |
0 |
T128 |
269094 |
642 |
0 |
0 |
T162 |
7286 |
14 |
0 |
0 |
T163 |
11945 |
31 |
0 |
0 |
T164 |
20806 |
81 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2654 |
0 |
0 |
T71 |
102097 |
166 |
0 |
0 |
T89 |
5010 |
9 |
0 |
0 |
T90 |
4135 |
18 |
0 |
0 |
T104 |
101678 |
168 |
0 |
0 |
T120 |
14077 |
23 |
0 |
0 |
T127 |
270598 |
653 |
0 |
0 |
T128 |
269094 |
620 |
0 |
0 |
T163 |
11945 |
51 |
0 |
0 |
T164 |
20806 |
43 |
0 |
0 |
T165 |
7204 |
12 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2526 |
0 |
0 |
T71 |
102097 |
121 |
0 |
0 |
T89 |
5010 |
27 |
0 |
0 |
T90 |
4135 |
20 |
0 |
0 |
T104 |
101678 |
139 |
0 |
0 |
T120 |
14077 |
12 |
0 |
0 |
T127 |
270598 |
679 |
0 |
0 |
T128 |
269094 |
660 |
0 |
0 |
T162 |
7286 |
11 |
0 |
0 |
T163 |
11945 |
28 |
0 |
0 |
T164 |
20806 |
59 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2439 |
0 |
0 |
T71 |
102097 |
103 |
0 |
0 |
T89 |
5010 |
13 |
0 |
0 |
T90 |
4135 |
12 |
0 |
0 |
T104 |
101678 |
126 |
0 |
0 |
T120 |
14077 |
10 |
0 |
0 |
T127 |
270598 |
666 |
0 |
0 |
T128 |
269094 |
661 |
0 |
0 |
T162 |
7286 |
6 |
0 |
0 |
T163 |
11945 |
33 |
0 |
0 |
T164 |
20806 |
53 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2490 |
0 |
0 |
T71 |
102097 |
114 |
0 |
0 |
T89 |
5010 |
8 |
0 |
0 |
T90 |
4135 |
15 |
0 |
0 |
T104 |
101678 |
116 |
0 |
0 |
T120 |
14077 |
11 |
0 |
0 |
T127 |
270598 |
703 |
0 |
0 |
T128 |
269094 |
689 |
0 |
0 |
T162 |
7286 |
1 |
0 |
0 |
T163 |
11945 |
11 |
0 |
0 |
T164 |
20806 |
50 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2493 |
0 |
0 |
T71 |
102097 |
95 |
0 |
0 |
T89 |
5010 |
21 |
0 |
0 |
T90 |
4135 |
14 |
0 |
0 |
T104 |
101678 |
117 |
0 |
0 |
T120 |
14077 |
10 |
0 |
0 |
T127 |
270598 |
708 |
0 |
0 |
T128 |
269094 |
665 |
0 |
0 |
T163 |
11945 |
48 |
0 |
0 |
T164 |
20806 |
61 |
0 |
0 |
T165 |
7204 |
52 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2390 |
0 |
0 |
T71 |
102097 |
151 |
0 |
0 |
T89 |
5010 |
10 |
0 |
0 |
T90 |
4135 |
16 |
0 |
0 |
T104 |
101678 |
121 |
0 |
0 |
T120 |
14077 |
23 |
0 |
0 |
T127 |
270598 |
688 |
0 |
0 |
T128 |
269094 |
630 |
0 |
0 |
T163 |
11945 |
21 |
0 |
0 |
T164 |
20806 |
69 |
0 |
0 |
T165 |
7204 |
17 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
464055259 |
2523 |
0 |
0 |
T71 |
102097 |
92 |
0 |
0 |
T89 |
5010 |
15 |
0 |
0 |
T90 |
4135 |
10 |
0 |
0 |
T104 |
101678 |
119 |
0 |
0 |
T120 |
14077 |
7 |
0 |
0 |
T127 |
270598 |
666 |
0 |
0 |
T128 |
269094 |
709 |
0 |
0 |
T163 |
11945 |
24 |
0 |
0 |
T164 |
20806 |
76 |
0 |
0 |
T165 |
7204 |
15 |
0 |
0 |