Group : spi_device_env_pkg::tpm_read_hw_reg_cg_wrap::tpm_read_hw_reg_cg
 
Group Instance : tpm_access_0
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_access_0
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_access_0
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_access_1
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_access_1
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_access_1
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_access_2
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_access_2
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_access_2
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_access_3
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_access_3
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_access_3
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_access_4
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_access_4
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_access_4
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_did_vid
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_did_vid
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_did_vid
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_hash_start
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_hash_start
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_hash_start
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_int_enable
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_int_enable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_int_enable
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_int_status
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_int_status
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_int_status
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_int_vector
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_int_vector
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_int_vector
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_intf_capability
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_intf_capability
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_intf_capability
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_rid
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_rid
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_rid
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
Group Instance : tpm_sts
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 
1      | 
100    | 
1      | 
64     | 
64     | 
 
Summary for Group Instance   tpm_sts
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 
1 | 
0 | 
1 | 
100.00 | 
Variables for Group Instance  tpm_sts
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_hit | 
1 | 
0 | 
1 | 
100.00 | 
100 | 
1 | 
1 | 
0 | 
 | 
 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
496 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T9 | 
30 | 
 | 
T29 | 
4 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
482 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T9 | 
22 | 
 | 
T92 | 
8 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
482 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T9 | 
26 | 
 | 
T29 | 
6 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
524 | 
1 | 
 | 
 | 
T1 | 
4 | 
 | 
T9 | 
16 | 
 | 
T29 | 
4 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
512 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T9 | 
16 | 
 | 
T12 | 
2 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2416 | 
1 | 
 | 
 | 
T1 | 
6 | 
 | 
T9 | 
62 | 
 | 
T12 | 
2 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2388 | 
1 | 
 | 
 | 
T1 | 
8 | 
 | 
T9 | 
60 | 
 | 
T12 | 
4 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2314 | 
1 | 
 | 
 | 
T1 | 
12 | 
 | 
T9 | 
66 | 
 | 
T12 | 
6 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2444 | 
1 | 
 | 
 | 
T1 | 
14 | 
 | 
T9 | 
78 | 
 | 
T12 | 
8 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2424 | 
1 | 
 | 
 | 
T1 | 
10 | 
 | 
T9 | 
82 | 
 | 
T12 | 
4 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
4 | 
1 | 
 | 
 | 
T306 | 
2 | 
 | 
T307 | 
2 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2418 | 
1 | 
 | 
 | 
T1 | 
8 | 
 | 
T9 | 
82 | 
 | 
T12 | 
6 | 
 
Summary for Variable cp_hit
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 
1 | 
0 | 
1 | 
100.00 | 
User Defined Bins for cp_hit
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| done | 
2196 | 
1 | 
 | 
 | 
T1 | 
2 | 
 | 
T2 | 
12 | 
 | 
T4 | 
6 | 
 
 
 
| 0% | 
10% | 
20% | 
30% | 
40% | 
50% | 
60% | 
70% | 
80% | 
90% | 
100% |