Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3421601	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4073050

1

T1

1799

T2

25

T3

898

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4084461	1			T1	1978		T2	1		T3	9
values[0x0]	1702439	1			T1	838		T2	14		T3	441
values[0x1]	1707751	1			T1	852		T2	20		T3	455

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2424030	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5070621

1

T1

2326

T2

27

T3

900

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	31357	1			T3	3		T6	3		T7	1
valid_sources[0x01]	27807	1			T3	5		T4	2		T6	4
valid_sources[0x02]	27319	1			T3	3		T6	2		T7	3
valid_sources[0x03]	30201	1			T1	14		T3	2		T6	8
valid_sources[0x04]	26916	1			T3	6		T6	9		T7	2
valid_sources[0x05]	27378	1			T1	327		T3	4		T6	11
valid_sources[0x06]	27985	1			T3	3		T6	6		T7	5
valid_sources[0x07]	26150	1			T3	4		T6	2		T7	2
valid_sources[0x08]	28049	1			T3	3		T6	12		T7	4
valid_sources[0x09]	30812	1			T3	4		T6	4		T7	6
valid_sources[0x0a]	25884	1			T1	1		T3	7		T6	6
valid_sources[0x0b]	29855	1			T1	55		T3	2		T6	8
valid_sources[0x0c]	28777	1			T3	4		T6	5		T7	4
valid_sources[0x0d]	31178	1			T3	5		T6	5		T7	3
valid_sources[0x0e]	25660	1			T3	2		T6	5		T7	1
valid_sources[0x0f]	28821	1			T1	25		T3	5		T6	5
valid_sources[0x10]	26938	1			T1	2		T3	4		T6	1
valid_sources[0x11]	27581	1			T3	3		T6	5		T7	5
valid_sources[0x12]	26186	1			T3	3		T6	2		T7	1
valid_sources[0x13]	31922	1			T3	3		T6	4		T7	1
valid_sources[0x14]	26443	1			T3	6		T6	10		T7	5
valid_sources[0x15]	32324	1			T2	3		T3	7		T6	4
valid_sources[0x16]	31321	1			T3	2		T6	6		T7	1
valid_sources[0x17]	33352	1			T3	7		T6	2		T7	4
valid_sources[0x18]	29601	1			T3	2		T6	5		T7	2
valid_sources[0x19]	29624	1			T1	28		T3	2		T6	6
valid_sources[0x1a]	29295	1			T6	6		T7	3		T9	3
valid_sources[0x1b]	28026	1			T3	5		T6	6		T7	6
valid_sources[0x1c]	28435	1			T3	2		T6	7		T7	2
valid_sources[0x1d]	26527	1			T1	2		T3	5		T6	6
valid_sources[0x1e]	32826	1			T2	21		T3	7		T6	7
valid_sources[0x1f]	31281	1			T1	75		T3	2		T6	8
valid_sources[0x20]	28927	1			T3	5		T6	9		T11	1
valid_sources[0x21]	28121	1			T3	6		T6	4		T7	1
valid_sources[0x22]	37792	1			T3	5		T6	7		T7	4
valid_sources[0x23]	28313	1			T3	3		T4	23		T6	3
valid_sources[0x24]	27815	1			T3	3		T6	6		T7	3
valid_sources[0x25]	31223	1			T6	5		T7	3		T11	3
valid_sources[0x26]	27682	1			T3	4		T6	7		T7	4
valid_sources[0x27]	29936	1			T3	2		T6	6		T7	4
valid_sources[0x28]	30515	1			T3	3		T6	1		T7	2
valid_sources[0x29]	26434	1			T3	4		T6	7		T7	1
valid_sources[0x2a]	34038	1			T6	5		T7	2		T9	4
valid_sources[0x2b]	30955	1			T3	3		T6	5		T7	3
valid_sources[0x2c]	29438	1			T3	5		T6	8		T7	1
valid_sources[0x2d]	29848	1			T3	2		T6	4		T7	7
valid_sources[0x2e]	34259	1			T3	3		T6	8		T7	3
valid_sources[0x2f]	28838	1			T3	1		T6	3		T9	1
valid_sources[0x30]	29194	1			T3	2		T6	6		T7	7
valid_sources[0x31]	31510	1			T3	1		T6	10		T7	4
valid_sources[0x32]	27433	1			T3	5		T6	6		T7	6
valid_sources[0x33]	28504	1			T3	2		T6	9		T7	6
valid_sources[0x34]	29175	1			T1	5		T3	3		T6	1
valid_sources[0x35]	28634	1			T3	3		T6	4		T7	7
valid_sources[0x36]	30121	1			T1	9		T3	4		T6	8
valid_sources[0x37]	30775	1			T3	3		T6	7		T7	5
valid_sources[0x38]	29275	1			T3	3		T6	11		T7	3
valid_sources[0x39]	27391	1			T3	3		T6	16		T7	4
valid_sources[0x3a]	27425	1			T3	5		T6	6		T7	4
valid_sources[0x3b]	30082	1			T3	1		T6	16		T7	4
valid_sources[0x3c]	29349	1			T3	2		T6	6		T9	1
valid_sources[0x3d]	29563	1			T6	4		T7	4		T11	4
valid_sources[0x3e]	29806	1			T1	1		T3	5		T6	4
valid_sources[0x3f]	28482	1			T3	4		T6	8		T7	6
valid_sources[0x40]	25566	1			T3	5		T6	9		T7	1
valid_sources[0x41]	29603	1			T3	3		T6	12		T7	4
valid_sources[0x42]	31121	1			T1	9		T3	4		T6	3
valid_sources[0x43]	30387	1			T1	59		T3	2		T6	2
valid_sources[0x44]	29089	1			T3	4		T6	6		T7	2
valid_sources[0x45]	27136	1			T3	6		T6	6		T7	6
valid_sources[0x46]	28245	1			T3	4		T6	5		T7	5
valid_sources[0x47]	26192	1			T1	7		T3	1		T6	5
valid_sources[0x48]	27271	1			T3	5		T6	1		T7	3
valid_sources[0x49]	28286	1			T3	2		T6	6		T7	3
valid_sources[0x4a]	31575	1			T3	5		T6	9		T7	1
valid_sources[0x4b]	26923	1			T3	7		T6	2		T7	5
valid_sources[0x4c]	26513	1			T1	1		T3	1		T6	3
valid_sources[0x4d]	30524	1			T3	6		T6	7		T7	3
valid_sources[0x4e]	26346	1			T3	5		T6	6		T7	3
valid_sources[0x4f]	28087	1			T1	1		T3	5		T6	4
valid_sources[0x50]	29015	1			T3	2		T6	2		T7	5
valid_sources[0x51]	27842	1			T3	5		T6	8		T7	3
valid_sources[0x52]	25926	1			T3	2		T6	2		T7	2
valid_sources[0x53]	37335	1			T3	7		T6	4		T7	2
valid_sources[0x54]	27273	1			T3	7		T6	4		T7	5
valid_sources[0x55]	25785	1			T3	7		T4	1		T6	7
valid_sources[0x56]	26953	1			T1	8		T2	2		T3	2
valid_sources[0x57]	31500	1			T3	3		T6	9		T7	4
valid_sources[0x58]	41462	1			T3	2		T6	5		T7	4
valid_sources[0x59]	26100	1			T2	2		T3	7		T6	5
valid_sources[0x5a]	31015	1			T3	3		T6	12		T7	2
valid_sources[0x5b]	27940	1			T3	1		T6	6		T7	3
valid_sources[0x5c]	28403	1			T3	5		T6	4		T7	5
valid_sources[0x5d]	27208	1			T3	1		T6	4		T7	6
valid_sources[0x5e]	30312	1			T3	7		T6	9		T7	5
valid_sources[0x5f]	26702	1			T1	1		T3	6		T6	11
valid_sources[0x60]	31626	1			T3	6		T6	4		T7	3
valid_sources[0x61]	28476	1			T3	3		T6	2		T7	6
valid_sources[0x62]	29371	1			T3	5		T6	12		T7	3
valid_sources[0x63]	27795	1			T3	4		T6	6		T7	5
valid_sources[0x64]	27188	1			T3	7		T6	13		T7	5
valid_sources[0x65]	28105	1			T3	7		T6	1		T7	2
valid_sources[0x66]	31590	1			T1	1		T6	8		T7	3
valid_sources[0x67]	27728	1			T3	5		T6	4		T7	4
valid_sources[0x68]	26893	1			T1	172		T3	6		T6	5
valid_sources[0x69]	29241	1			T3	3		T6	9		T7	6
valid_sources[0x6a]	40619	1			T3	3		T6	6		T7	5
valid_sources[0x6b]	26947	1			T3	2		T6	7		T7	1
valid_sources[0x6c]	29586	1			T3	3		T6	8		T7	2
valid_sources[0x6d]	29990	1			T3	4		T6	6		T7	4
valid_sources[0x6e]	26206	1			T1	43		T3	2		T6	8
valid_sources[0x6f]	29745	1			T1	4		T3	1		T6	6
valid_sources[0x70]	29527	1			T3	4		T6	1		T7	6
valid_sources[0x71]	30809	1			T1	2		T3	4		T6	6
valid_sources[0x72]	27982	1			T1	2		T3	1		T6	2
valid_sources[0x73]	27480	1			T1	808		T3	2		T6	6
valid_sources[0x74]	27376	1			T1	56		T3	6		T6	8
valid_sources[0x75]	27907	1			T3	4		T6	5		T7	5
valid_sources[0x76]	35055	1			T3	2		T6	12		T7	2
valid_sources[0x77]	25677	1			T3	3		T6	1		T7	4
valid_sources[0x78]	30473	1			T3	3		T6	9		T7	2
valid_sources[0x79]	30580	1			T3	1		T6	10		T7	2
valid_sources[0x7a]	27044	1			T3	5		T6	10		T7	4
valid_sources[0x7b]	26166	1			T3	5		T6	8		T7	4
valid_sources[0x7c]	27421	1			T3	1		T6	7		T7	7
valid_sources[0x7d]	26860	1			T3	4		T4	2		T6	3
valid_sources[0x7e]	27582	1			T3	4		T6	3		T7	5
valid_sources[0x7f]	28652	1			T3	5		T6	9		T7	2
valid_sources[0x80]	46666	1			T2	3		T3	4		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

980929

1

T1

636

T2

1

T3

4

values[0x0]

all_enables

biggest_size

1555543

1

T1

603

T2

9

T3

441

values[0x1]

all_enables

biggest_size

1536578

1

T1

560

T2

15

T3

453