Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3447384

1

T1

1869

T2

10

T3

7

full_word

4074540

1

T1

1799

T2

25

T3

898

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7521524	1			T1	3668		T2	35		T3	905
auto[TlIntgErrCmd]	137	1			T70	6		T105	7		T106	13
auto[TlIntgErrData]	134	1			T70	10		T105	1		T106	11
auto[TlIntgErrBoth]	129	1			T70	14		T105	2		T106	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4089784

1

T1

1978

T2

1

T3

9

auto[1]

3432140

1

T1

1690

T2

34

T3

896

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3108287	1			T1	1342		T3	5		T5	88
auto[TlIntgErrNone]	partial	auto[1]	338730	1			T1	527		T2	10		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	981298	1			T1	636		T2	1		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	3093209	1			T1	1163		T2	24		T3	894
auto[TlIntgErrCmd]	partial	auto[0]	65	1			T70	4		T105	7		T106	5
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T70	2		T106	7		T167	5
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T167	1		T169	1		T168	1
auto[TlIntgErrCmd]	full_word	auto[1]	9	1			T106	1		T169	1		T170	2
auto[TlIntgErrData]	partial	auto[0]	68	1			T70	3		T105	1		T106	9
auto[TlIntgErrData]	partial	auto[1]	56	1			T70	6		T106	1		T167	2
auto[TlIntgErrData]	full_word	auto[0]	5	1			T106	1		T167	1		T143	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T70	1		T143	1		T144	2
auto[TlIntgErrBoth]	partial	auto[0]	55	1			T70	12		T105	1		T106	3
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T70	2		T105	1		T106	1
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T171	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T106	2		T167	1		T170	1