Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	611231051	3273095	0	0
gen_wmask[1].MaskCheckPortA_A	611231051	3273095	0	0
gen_wmask[2].MaskCheckPortA_A	611231051	3273095	0	0
gen_wmask[3].MaskCheckPortA_A	611231051	3273095	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611231051	3273095	0	0
T1	273643	2701	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	52	0	0
T11	25955	832	0	0
T12	0	16440	0	0
T13	0	832	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	7177	0	0
T28	0	5420	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611231051	3273095	0	0
T1	273643	2701	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	52	0	0
T11	25955	832	0	0
T12	0	16440	0	0
T13	0	832	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	7177	0	0
T28	0	5420	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611231051	3273095	0	0
T1	273643	2701	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	52	0	0
T11	25955	832	0	0
T12	0	16440	0	0
T13	0	832	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	7177	0	0
T28	0	5420	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	611231051	3273095	0	0
T1	273643	2701	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	52	0	0
T11	25955	832	0	0
T12	0	16440	0	0
T13	0	832	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	7177	0	0
T28	0	5420	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	466500318	2025632	0	0
gen_wmask[1].MaskCheckPortA_A	466500318	2025632	0	0
gen_wmask[2].MaskCheckPortA_A	466500318	2025632	0	0
gen_wmask[3].MaskCheckPortA_A	466500318	2025632	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2025632	0	0
T1	101313	558	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	0	0	0
T11	0	832	0	0
T12	0	11096	0	0
T13	0	832	0	0
T27	0	2159	0	0
T28	0	1700	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2025632	0	0
T1	101313	558	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	0	0	0
T11	0	832	0	0
T12	0	11096	0	0
T13	0	832	0	0
T27	0	2159	0	0
T28	0	1700	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2025632	0	0
T1	101313	558	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	0	0	0
T11	0	832	0	0
T12	0	11096	0	0
T13	0	832	0	0
T27	0	2159	0	0
T28	0	1700	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2025632	0	0
T1	101313	558	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	0	0	0
T11	0	832	0	0
T12	0	11096	0	0
T13	0	832	0	0
T27	0	2159	0	0
T28	0	1700	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	144730733	1247463	0	0
gen_wmask[1].MaskCheckPortA_A	144730733	1247463	0	0
gen_wmask[2].MaskCheckPortA_A	144730733	1247463	0	0
gen_wmask[3].MaskCheckPortA_A	144730733	1247463	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	1247463	0	0
T1	172330	2143	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	5344	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	5018	0	0
T28	0	3720	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	1247463	0	0
T1	172330	2143	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	5344	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	5018	0	0
T28	0	3720	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	1247463	0	0
T1	172330	2143	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	5344	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	5018	0	0
T28	0	3720	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	1247463	0	0
T1	172330	2143	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	5344	0	0
T16	0	7881	0	0
T24	0	2682	0	0
T27	0	5018	0	0
T28	0	3720	0	0
T30	0	14444	0	0
T31	0	47	0	0
T49	0	10	0	0