Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468701915	2803163	0	0
DepthKnown_A	468701915	468570747	0	0
RvalidKnown_A	468701915	468570747	0	0
WreadyKnown_A	468701915	468570747	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	2803163	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	1663	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	0	0	0
T11	16756	1663	0	0
T12	267808	15813	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T15	0	1663	0	0
T16	0	8318	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468701915	3033796	0	0
DepthKnown_A	468701915	468570747	0	0
RvalidKnown_A	468701915	468570747	0	0
WreadyKnown_A	468701915	468570747	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	3033796	0	0
T3	118642	3734	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	3806	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	0	0	0
T11	16756	832	0	0
T12	267808	25159	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	6656	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468701915	186550	0	0
DepthKnown_A	468701915	468570747	0	0
RvalidKnown_A	468701915	468570747	0	0
WreadyKnown_A	468701915	468570747	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	186550	0	0
T1	101313	555	0	0
T2	2726	0	0	0
T3	118642	0	0	0
T4	7690	0	0	0
T5	11993	0	0	0
T6	434067	0	0	0
T7	10596	0	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T12	0	1216	0	0
T16	0	354	0	0
T24	0	312	0	0
T26	0	1295	0	0
T27	0	1292	0	0
T28	0	952	0	0
T30	0	1594	0	0
T31	0	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468701915	406772	0	0
DepthKnown_A	468701915	468570747	0	0
RvalidKnown_A	468701915	468570747	0	0
WreadyKnown_A	468701915	468570747	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	406772	0	0
T1	101313	555	0	0
T2	2726	0	0	0
T3	118642	0	0	0
T4	7690	0	0	0
T5	11993	0	0	0
T6	434067	0	0	0
T7	10596	0	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T12	0	5627	0	0
T16	0	484	0	0
T24	0	1376	0	0
T26	0	1295	0	0
T27	0	1292	0	0
T28	0	952	0	0
T30	0	6691	0	0
T31	0	49	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468701915	5855178	0	0
DepthKnown_A	468701915	468570747	0	0
RvalidKnown_A	468701915	468570747	0	0
WreadyKnown_A	468701915	468570747	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	5855178	0	0
T1	101313	3128	0	0
T2	2726	35	0	0
T3	118642	73	0	0
T4	7690	35	0	0
T5	11993	223	0	0
T6	434067	749	0	0
T7	10596	69	0	0
T8	1153	7	0	0
T9	171414	777	0	0
T10	1121	133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	468701915	11196006	0	0
DepthKnown_A	468701915	468570747	0	0
RvalidKnown_A	468701915	468570747	0	0
WreadyKnown_A	468701915	468570747	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	11196006	0	0
T1	101313	3113	0	0
T2	2726	91	0	0
T3	118642	275	0	0
T4	7690	35	0	0
T5	11993	223	0	0
T6	434067	3218	0	0
T7	10596	69	0	0
T8	1153	7	0	0
T9	171414	3428	0	0
T10	1121	133	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	468701915	468570747	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0