Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T12,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T16,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T30
1	0	Covered	T12,T16,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T12,T16,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T27

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	755961784	609869655	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	755961784	3647834	0	0
GntImpliesValid_A	755961784	3647834	0	0
GrantKnown_A	755961784	609869655	0	0
IdxKnown_A	755961784	609869655	0	0
IndexIsCorrect_A	755961784	3647834	0	0
LockArbDecision_A	755961784	0	0	0
NoReadyValidNoGrant_A	755961784	0	0	0
ReadyAndValidImplyGrant_A	755961784	3647834	0	0
ReqAndReadyImplyGrant_A	755961784	3647834	0	0
ReqImpliesValid_A	755961784	3647834	0	0
ReqStaysHighUntilGranted0_M	755961784	0	0	0
RoundRobin_A	755961784	1	0	955
ValidKnown_A	755961784	609869655	0	0
gen_data_port_assertion.DataFlow_A	755961784	3647834	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	609869655	0	0
T1	273643	269583	0	0
T2	3518	3454	0	0
T3	332144	224265	0	0
T4	9274	8388	0	0
T5	47993	29915	0	0
T6	539893	486833	0	0
T7	61060	35774	0	0
T8	1153	1067	0	0
T9	415608	288804	0	0
T10	2033	1489	0	0
T11	51910	25872	0	0
T12	539197	531166	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	609869655	0	0
T1	273643	269583	0	0
T2	3518	3454	0	0
T3	332144	224265	0	0
T4	9274	8388	0	0
T5	47993	29915	0	0
T6	539893	486833	0	0
T7	61060	35774	0	0
T8	1153	1067	0	0
T9	415608	288804	0	0
T10	2033	1489	0	0
T11	51910	25872	0	0
T12	539197	531166	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	609869655	0	0
T1	273643	269583	0	0
T2	3518	3454	0	0
T3	332144	224265	0	0
T4	9274	8388	0	0
T5	47993	29915	0	0
T6	539893	486833	0	0
T7	61060	35774	0	0
T8	1153	1067	0	0
T9	415608	288804	0	0
T10	2033	1489	0	0
T11	51910	25872	0	0
T12	539197	531166	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	1	0	955
T56	108051	1	0	1
T57	1189	0	0	1
T58	65774	0	0	1
T59	99692	0	0	1
T60	72212	0	0	1
T61	20505	0	0	1
T62	21986	0	0	1
T63	1263	0	0	1
T64	4012	0	0	1
T65	562117	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	609869655	0	0
T1	273643	269583	0	0
T2	3518	3454	0	0
T3	332144	224265	0	0
T4	9274	8388	0	0
T5	47993	29915	0	0
T6	539893	486833	0	0
T7	61060	35774	0	0
T8	1153	1067	0	0
T9	415608	288804	0	0
T10	2033	1489	0	0
T11	51910	25872	0	0
T12	539197	531166	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	755961784	3647834	0	0
T1	273643	3866	0	0
T2	3518	0	0	0
T3	225393	832	0	0
T4	8482	0	0	0
T5	29993	832	0	0
T6	486980	832	0	0
T7	35828	832	0	0
T8	1153	0	0	0
T9	293511	0	0	0
T10	1577	65	0	0
T11	25955	832	0	0
T12	539197	18910	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	7327	0	0
T27	201457	10842	0	0
T28	429887	8216	0	0
T29	25701	0	0	0
T30	0	16672	0	0
T31	0	64	0	0
T32	100	0	0	0
T37	0	3461	0	0
T41	0	6721	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T12,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Unreachable
1	1	Covered	T1,T10,T12

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T10,T12
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144730733	25992175	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	144730733	610585	0	0
GntImpliesValid_A	144730733	610585	0	0
GrantKnown_A	144730733	25992175	0	0
IdxKnown_A	144730733	25992175	0	0
IndexIsCorrect_A	144730733	610585	0	0
LockArbDecision_A	144730733	0	0	0
NoReadyValidNoGrant_A	144730733	0	0	0
ReadyAndValidImplyGrant_A	144730733	610585	0	0
ReqAndReadyImplyGrant_A	144730733	610585	0	0
ReqImpliesValid_A	144730733	610585	0	0
ReqStaysHighUntilGranted0_M	144730733	0	0	0
RoundRobin_A	144730733	0	0	0
ValidKnown_A	144730733	25992175	0	0
gen_data_port_assertion.DataFlow_A	144730733	610585	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	25992175	0	0
T1	172330	168368	0	0
T2	792	792	0	0
T3	106751	0	0	0
T4	792	792	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	117456	0	0
T10	456	456	0	0
T11	25955	0	0	0
T12	0	101640	0	0
T27	0	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	25992175	0	0
T1	172330	168368	0	0
T2	792	792	0	0
T3	106751	0	0	0
T4	792	792	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	117456	0	0
T10	456	456	0	0
T11	25955	0	0	0
T12	0	101640	0	0
T27	0	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	25992175	0	0
T1	172330	168368	0	0
T2	792	792	0	0
T3	106751	0	0	0
T4	792	792	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	117456	0	0
T10	456	456	0	0
T11	25955	0	0	0
T12	0	101640	0	0
T27	0	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	25992175	0	0
T1	172330	168368	0	0
T2	792	792	0	0
T3	106751	0	0	0
T4	792	792	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	117456	0	0
T10	456	456	0	0
T11	25955	0	0	0
T12	0	101640	0	0
T27	0	194800	0	0
T28	0	422880	0	0
T29	0	24720	0	0
T32	0	72	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	610585	0	0
T1	172330	2753	0	0
T2	792	0	0	0
T3	106751	0	0	0
T4	792	0	0	0
T5	18000	0	0	0
T6	52913	0	0	0
T7	25232	0	0	0
T9	122097	0	0	0
T10	456	52	0	0
T11	25955	0	0	0
T12	0	4327	0	0
T26	0	5463	0	0
T27	0	7391	0	0
T28	0	5564	0	0
T30	0	6257	0	0
T31	0	64	0	0
T37	0	1906	0	0
T41	0	5140	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T16,T30

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T12,T16,T30
1	0	Covered	T12,T16,T30

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Unreachable
1	1	Covered	T12,T16,T30

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T16,T30
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T6

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T30
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T12,T16,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	144730733	117463227	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	144730733	838539	0	0
GntImpliesValid_A	144730733	838539	0	0
GrantKnown_A	144730733	117463227	0	0
IdxKnown_A	144730733	117463227	0	0
IndexIsCorrect_A	144730733	838539	0	0
LockArbDecision_A	144730733	0	0	0
NoReadyValidNoGrant_A	144730733	0	0	0
ReadyAndValidImplyGrant_A	144730733	838539	0	0
ReqAndReadyImplyGrant_A	144730733	838539	0	0
ReqImpliesValid_A	144730733	838539	0	0
ReqStaysHighUntilGranted0_M	144730733	0	0	0
RoundRobin_A	144730733	0	0	0
ValidKnown_A	144730733	117463227	0	0
gen_data_port_assertion.DataFlow_A	144730733	838539	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	117463227	0	0
T3	106751	105720	0	0
T4	792	0	0	0
T5	18000	18000	0	0
T6	52913	52832	0	0
T7	25232	25232	0	0
T9	122097	0	0	0
T10	456	0	0	0
T11	25955	25872	0	0
T12	539197	429526	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	0	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	117463227	0	0
T3	106751	105720	0	0
T4	792	0	0	0
T5	18000	18000	0	0
T6	52913	52832	0	0
T7	25232	25232	0	0
T9	122097	0	0	0
T10	456	0	0	0
T11	25955	25872	0	0
T12	539197	429526	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	0	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	117463227	0	0
T3	106751	105720	0	0
T4	792	0	0	0
T5	18000	18000	0	0
T6	52913	52832	0	0
T7	25232	25232	0	0
T9	122097	0	0	0
T10	456	0	0	0
T11	25955	25872	0	0
T12	539197	429526	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	0	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	117463227	0	0
T3	106751	105720	0	0
T4	792	0	0	0
T5	18000	18000	0	0
T6	52913	52832	0	0
T7	25232	25232	0	0
T9	122097	0	0	0
T10	456	0	0	0
T11	25955	25872	0	0
T12	539197	429526	0	0
T13	0	10400	0	0
T14	0	28296	0	0
T15	0	28530	0	0
T16	0	456821	0	0
T27	201457	0	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	144730733	838539	0	0
T12	539197	2241	0	0
T13	10400	0	0	0
T14	28296	0	0	0
T15	28530	0	0	0
T16	458722	7881	0	0
T18	0	6404	0	0
T24	0	2682	0	0
T26	0	1864	0	0
T27	201457	0	0	0
T28	429887	0	0	0
T29	25701	0	0	0
T30	0	10415	0	0
T32	100	0	0	0
T37	0	1555	0	0
T41	0	1581	0	0
T48	128	0	0	0
T49	0	10	0	0
T55	0	4	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T27

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T10,T12
1	0	Covered	T1,T3,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T5
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	466500318	466414253	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	466500318	2198710	0	0
GntImpliesValid_A	466500318	2198710	0	0
GrantKnown_A	466500318	466414253	0	0
IdxKnown_A	466500318	466414253	0	0
IndexIsCorrect_A	466500318	2198710	0	0
LockArbDecision_A	466500318	0	0	0
NoReadyValidNoGrant_A	466500318	0	0	0
ReadyAndValidImplyGrant_A	466500318	2198710	0	0
ReqAndReadyImplyGrant_A	466500318	2198710	0	0
ReqImpliesValid_A	466500318	2198710	0	0
ReqStaysHighUntilGranted0_M	466500318	0	0	0
RoundRobin_A	466500318	1	0	955
ValidKnown_A	466500318	466414253	0	0
gen_data_port_assertion.DataFlow_A	466500318	2198710	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	466414253	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	466414253	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	466414253	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	1	0	955
T56	108051	1	0	1
T57	1189	0	0	1
T58	65774	0	0	1
T59	99692	0	0	1
T60	72212	0	0	1
T61	20505	0	0	1
T62	21986	0	0	1
T63	1263	0	0	1
T64	4012	0	0	1
T65	562117	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	466414253	0	0
T1	101313	101215	0	0
T2	2726	2662	0	0
T3	118642	118545	0	0
T4	7690	7596	0	0
T5	11993	11915	0	0
T6	434067	434001	0	0
T7	10596	10542	0	0
T8	1153	1067	0	0
T9	171414	171348	0	0
T10	1121	1033	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	466500318	2198710	0	0
T1	101313	1113	0	0
T2	2726	0	0	0
T3	118642	832	0	0
T4	7690	0	0	0
T5	11993	832	0	0
T6	434067	832	0	0
T7	10596	832	0	0
T8	1153	0	0	0
T9	171414	0	0	0
T10	1121	13	0	0
T11	0	832	0	0
T12	0	12342	0	0
T27	0	3451	0	0
T28	0	2652	0	0