Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3023050	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

3886480

1

T1

7603

T2

902

T3

909

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3731234	1			T1	1040		T2	65		T3	2968
values[0x0]	1588764	1			T1	3550		T2	430		T3	440
values[0x1]	1589532	1			T1	3506		T2	460		T3	425

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2158387	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4751143

1

T1

7718

T2

910

T3

1863

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28981	1			T1	31		T3	14		T5	46
valid_sources[0x01]	26185	1			T1	27		T3	12		T7	8
valid_sources[0x02]	28540	1			T1	81		T3	14		T5	323
valid_sources[0x03]	29471	1			T1	32		T3	15		T7	10
valid_sources[0x04]	26546	1			T1	42		T3	7		T7	14
valid_sources[0x05]	27885	1			T1	35		T3	20		T5	24
valid_sources[0x06]	25598	1			T1	2		T3	21		T7	14
valid_sources[0x07]	27947	1			T1	56		T3	17		T5	10
valid_sources[0x08]	23929	1			T1	8		T3	23		T7	7
valid_sources[0x09]	24248	1			T1	21		T3	10		T5	172
valid_sources[0x0a]	26827	1			T1	9		T3	23		T7	8
valid_sources[0x0b]	26665	1			T1	62		T3	15		T7	9
valid_sources[0x0c]	23597	1			T1	21		T3	13		T5	197
valid_sources[0x0d]	24036	1			T1	15		T3	14		T5	10
valid_sources[0x0e]	27296	1			T1	1		T3	7		T7	5
valid_sources[0x0f]	26430	1			T1	141		T3	12		T5	1
valid_sources[0x10]	28193	1			T1	32		T3	17		T7	9
valid_sources[0x11]	28770	1			T1	45		T3	16		T7	7
valid_sources[0x12]	25641	1			T1	92		T3	15		T7	7
valid_sources[0x13]	24136	1			T1	70		T3	9		T7	7
valid_sources[0x14]	22806	1			T1	1		T3	27		T7	9
valid_sources[0x15]	25180	1			T1	57		T3	4		T5	280
valid_sources[0x16]	24401	1			T1	27		T3	11		T5	1
valid_sources[0x17]	24618	1			T1	6		T3	19		T7	3
valid_sources[0x18]	23986	1			T1	7		T3	13		T5	151
valid_sources[0x19]	27834	1			T1	46		T3	14		T5	202
valid_sources[0x1a]	37413	1			T1	19		T3	10		T7	6
valid_sources[0x1b]	25143	1			T1	78		T3	15		T7	16
valid_sources[0x1c]	24298	1			T1	26		T3	19		T7	8
valid_sources[0x1d]	24966	1			T1	58		T3	14		T7	4
valid_sources[0x1e]	24975	1			T1	16		T3	10		T7	10
valid_sources[0x1f]	25079	1			T1	59		T3	12		T5	29
valid_sources[0x20]	26411	1			T1	4		T3	24		T7	8
valid_sources[0x21]	25389	1			T1	1		T3	12		T4	1
valid_sources[0x22]	22895	1			T1	9		T3	13		T5	2
valid_sources[0x23]	25053	1			T1	22		T3	10		T7	12
valid_sources[0x24]	34209	1			T1	26		T3	13		T7	10
valid_sources[0x25]	25168	1			T1	13		T2	5		T3	12
valid_sources[0x26]	25722	1			T1	29		T3	12		T7	7
valid_sources[0x27]	24947	1			T1	1		T3	19		T7	11
valid_sources[0x28]	31099	1			T1	36		T3	15		T7	26
valid_sources[0x29]	24228	1			T1	44		T3	19		T5	101
valid_sources[0x2a]	26331	1			T1	17		T3	14		T5	348
valid_sources[0x2b]	22819	1			T1	7		T3	14		T7	8
valid_sources[0x2c]	24997	1			T1	27		T3	16		T5	1
valid_sources[0x2d]	24194	1			T1	15		T3	17		T7	9
valid_sources[0x2e]	26162	1			T1	26		T3	26		T7	14
valid_sources[0x2f]	24527	1			T1	100		T3	7		T7	12
valid_sources[0x30]	24310	1			T1	59		T3	10		T7	5
valid_sources[0x31]	25727	1			T1	50		T3	26		T5	358
valid_sources[0x32]	26417	1			T1	6		T3	18		T5	114
valid_sources[0x33]	30403	1			T1	5		T3	14		T7	10
valid_sources[0x34]	29862	1			T1	17		T3	9		T5	539
valid_sources[0x35]	22106	1			T1	37		T3	29		T5	4
valid_sources[0x36]	30256	1			T1	10		T2	23		T3	22
valid_sources[0x37]	28014	1			T1	31		T3	15		T5	556
valid_sources[0x38]	26120	1			T1	4		T3	8		T7	7
valid_sources[0x39]	30654	1			T1	53		T3	7		T5	475
valid_sources[0x3a]	26271	1			T1	17		T3	14		T5	1
valid_sources[0x3b]	26162	1			T1	13		T3	16		T7	6
valid_sources[0x3c]	26739	1			T1	35		T3	13		T5	7
valid_sources[0x3d]	26168	1			T1	19		T3	21		T7	14
valid_sources[0x3e]	23216	1			T1	13		T3	18		T7	6
valid_sources[0x3f]	24009	1			T1	16		T2	4		T3	21
valid_sources[0x40]	25006	1			T1	48		T3	16		T7	13
valid_sources[0x41]	27451	1			T1	26		T3	19		T7	15
valid_sources[0x42]	25250	1			T1	22		T3	19		T5	1
valid_sources[0x43]	24207	1			T1	15		T3	9		T7	9
valid_sources[0x44]	24526	1			T1	31		T3	16		T7	4
valid_sources[0x45]	34074	1			T1	28		T3	10		T5	76
valid_sources[0x46]	26113	1			T1	26		T3	8		T5	421
valid_sources[0x47]	24140	1			T1	23		T3	13		T7	10
valid_sources[0x48]	25260	1			T1	4		T3	16		T7	11
valid_sources[0x49]	24170	1			T1	59		T3	22		T7	9
valid_sources[0x4a]	23586	1			T1	11		T3	15		T7	14
valid_sources[0x4b]	25644	1			T1	5		T3	15		T5	770
valid_sources[0x4c]	27390	1			T1	7		T3	13		T7	3
valid_sources[0x4d]	24095	1			T1	57		T3	10		T5	85
valid_sources[0x4e]	24590	1			T1	21		T3	13		T5	3
valid_sources[0x4f]	26359	1			T3	21		T5	3		T7	12
valid_sources[0x50]	23289	1			T1	19		T3	18		T7	7
valid_sources[0x51]	26539	1			T1	3		T2	162		T3	23
valid_sources[0x52]	27715	1			T1	12		T3	16		T5	375
valid_sources[0x53]	24675	1			T1	32		T3	17		T7	4
valid_sources[0x54]	26679	1			T1	14		T2	56		T3	14
valid_sources[0x55]	28425	1			T1	22		T3	14		T7	11
valid_sources[0x56]	30740	1			T1	20		T3	19		T7	9
valid_sources[0x57]	25078	1			T1	36		T2	67		T3	16
valid_sources[0x58]	26960	1			T3	10		T7	14		T10	1
valid_sources[0x59]	28006	1			T1	19		T3	10		T5	4
valid_sources[0x5a]	24880	1			T1	56		T3	11		T5	2
valid_sources[0x5b]	24245	1			T1	34		T3	12		T5	3
valid_sources[0x5c]	24333	1			T1	42		T3	8		T5	2
valid_sources[0x5d]	27312	1			T1	21		T3	15		T5	14
valid_sources[0x5e]	28681	1			T1	70		T3	11		T7	8
valid_sources[0x5f]	25119	1			T1	10		T3	10		T7	3
valid_sources[0x60]	28926	1			T1	75		T3	21		T5	236
valid_sources[0x61]	27817	1			T1	38		T2	26		T3	15
valid_sources[0x62]	25858	1			T1	72		T3	11		T5	127
valid_sources[0x63]	27362	1			T1	23		T3	18		T7	14
valid_sources[0x64]	24734	1			T1	60		T3	5		T5	18
valid_sources[0x65]	26849	1			T1	53		T3	15		T7	10
valid_sources[0x66]	25547	1			T1	5		T3	13		T5	731
valid_sources[0x67]	25629	1			T1	61		T3	14		T7	8
valid_sources[0x68]	28553	1			T3	21		T7	10		T10	9
valid_sources[0x69]	24629	1			T1	63		T3	15		T5	3
valid_sources[0x6a]	26245	1			T1	20		T3	17		T7	12
valid_sources[0x6b]	27633	1			T1	2		T3	21		T5	1
valid_sources[0x6c]	27969	1			T1	104		T3	15		T5	154
valid_sources[0x6d]	27439	1			T1	28		T3	13		T5	3
valid_sources[0x6e]	26709	1			T1	66		T3	13		T7	10
valid_sources[0x6f]	23862	1			T1	12		T3	13		T7	13
valid_sources[0x70]	22613	1			T1	38		T3	18		T5	1
valid_sources[0x71]	26082	1			T1	21		T3	12		T7	10
valid_sources[0x72]	25631	1			T1	83		T3	14		T5	22
valid_sources[0x73]	24014	1			T1	39		T3	18		T7	7
valid_sources[0x74]	35657	1			T1	47		T3	10		T5	2
valid_sources[0x75]	24186	1			T1	89		T3	17		T5	78
valid_sources[0x76]	25685	1			T1	41		T3	9		T7	12
valid_sources[0x77]	31097	1			T1	43		T3	22		T5	572
valid_sources[0x78]	53030	1			T1	41		T3	20		T5	1
valid_sources[0x79]	23112	1			T1	1		T3	15		T7	8
valid_sources[0x7a]	30196	1			T1	33		T3	14		T7	4
valid_sources[0x7b]	25531	1			T1	13		T3	18		T5	4
valid_sources[0x7c]	29445	1			T1	35		T3	16		T4	2
valid_sources[0x7d]	24369	1			T1	36		T3	14		T7	9
valid_sources[0x7e]	25181	1			T1	35		T3	11		T7	7
valid_sources[0x7f]	24049	1			T1	9		T3	9		T7	3
valid_sources[0x80]	25155	1			T1	44		T3	11		T7	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

989142

1

T1

592

T2

26

T3

271

values[0x0]

all_enables

biggest_size

1459696

1

T1

3534

T2

422

T3

331

values[0x1]

all_enables

biggest_size

1437642

1

T1

3477

T2

454

T3

307