Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3048417

1

T1

493

T2

53

T3

2924

full_word

3888026

1

T1

7603

T2

902

T3

909

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	6936103	1			T1	8096		T2	955		T3	3833
auto[TlIntgErrCmd]	136	1			T100	4		T101	2		T103	13
auto[TlIntgErrData]	96	1			T100	4		T101	3		T103	10
auto[TlIntgErrBoth]	108	1			T100	2		T101	5		T103	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3736882

1

T1

1040

T2

65

T3

2968

auto[1]

3199561

1

T1

7056

T2

890

T3

865

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	2747198	1			T1	448		T2	39		T3	2697
auto[TlIntgErrNone]	partial	auto[1]	300908	1			T1	45		T2	14		T3	227
auto[TlIntgErrNone]	full_word	auto[0]	989545	1			T1	592		T2	26		T3	271
auto[TlIntgErrNone]	full_word	auto[1]	2898452	1			T1	7011		T2	876		T3	638
auto[TlIntgErrCmd]	partial	auto[0]	40	1			T100	2		T101	1		T103	3
auto[TlIntgErrCmd]	partial	auto[1]	80	1			T100	2		T101	1		T103	6
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T103	1		T112	1		T154	2
auto[TlIntgErrCmd]	full_word	auto[1]	8	1			T103	3		T155	1		T184	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T100	1		T101	2		T103	5
auto[TlIntgErrData]	partial	auto[1]	46	1			T100	2		T101	1		T103	5
auto[TlIntgErrData]	full_word	auto[0]	5	1			T154	1		T183	1		T155	1
auto[TlIntgErrData]	full_word	auto[1]	2	1			T100	1		T183	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T101	1		T103	4		T116	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T100	2		T101	4		T103	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T184	1		T185	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T186	1		T187	1		T188	1