Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	407442214	2734787	0	0
DepthKnown_A	407442214	407314929	0	0
RvalidKnown_A	407442214	407314929	0	0
WreadyKnown_A	407442214	407314929	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	2734787	0	0
T1	268364	9163	0	0
T2	7877	1663	0	0
T3	216893	0	0	0
T4	1146	0	0	0
T5	795737	0	0	0
T6	1549	0	0	0
T7	21728	0	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	1663	0	0
T13	0	1663	0	0
T14	0	1663	0	0
T15	0	1663	0	0
T16	0	7498	0	0
T17	0	1663	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	407442214	3012270	0	0
DepthKnown_A	407442214	407314929	0	0
RvalidKnown_A	407442214	407314929	0	0
WreadyKnown_A	407442214	407314929	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	3012270	0	0
T1	268364	21187	0	0
T2	7877	832	0	0
T3	216893	0	0	0
T4	1146	0	0	0
T5	795737	0	0	0
T6	1549	0	0	0
T7	21728	0	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0
T15	0	832	0	0
T16	0	7028	0	0
T17	0	832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	407442214	180411	0	0
DepthKnown_A	407442214	407314929	0	0
RvalidKnown_A	407442214	407314929	0	0
WreadyKnown_A	407442214	407314929	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	180411	0	0
T1	268364	193	0	0
T2	7877	0	0	0
T3	216893	220	0	0
T4	1146	0	0	0
T5	795737	799	0	0
T6	1549	0	0	0
T7	21728	47	0	0
T8	418272	0	0	0
T9	1053	0	0	0
T10	34745	0	0	0
T16	0	382	0	0
T27	0	486	0	0
T28	0	49	0	0
T29	0	279	0	0
T31	0	932	0	0
T42	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	407442214	393838	0	0
DepthKnown_A	407442214	407314929	0	0
RvalidKnown_A	407442214	407314929	0	0
WreadyKnown_A	407442214	407314929	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	393838	0	0
T1	268364	869	0	0
T2	7877	0	0	0
T3	216893	220	0	0
T4	1146	0	0	0
T5	795737	2559	0	0
T6	1549	0	0	0
T7	21728	47	0	0
T8	418272	0	0	0
T9	1053	0	0	0
T10	34745	0	0	0
T16	0	1734	0	0
T27	0	2142	0	0
T28	0	49	0	0
T29	0	1368	0	0
T31	0	4162	0	0
T42	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	407442214	5330365	0	0
DepthKnown_A	407442214	407314929	0	0
RvalidKnown_A	407442214	407314929	0	0
WreadyKnown_A	407442214	407314929	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	5330365	0	0
T1	268364	1281	0	0
T2	7877	123	0	0
T3	216893	3634	0	0
T4	1146	14	0	0
T5	795737	12887	0	0
T6	1549	18	0	0
T7	21728	2261	0	0
T8	418272	68	0	0
T9	1053	15	0	0
T10	34745	981	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	407442214	11830102	0	0
DepthKnown_A	407442214	407314929	0	0
RvalidKnown_A	407442214	407314929	0	0
WreadyKnown_A	407442214	407314929	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	11830102	0	0
T1	268364	5534	0	0
T2	7877	410	0	0
T3	216893	3613	0	0
T4	1146	81	0	0
T5	795737	39055	0	0
T6	1549	18	0	0
T7	21728	2261	0	0
T8	418272	68	0	0
T9	1053	15	0	0
T10	34745	981	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	407442214	407314929	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0