Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T7
1	0	Covered	T3,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Unreachable
1	1	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T16,T29
1	0	Covered	T1,T16,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Covered	T1,T16,T29

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	692081653	547231295	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	692081653	3514184	0	0
GntImpliesValid_A	692081653	3514184	0	0
GrantKnown_A	692081653	547231295	0	0
IdxKnown_A	692081653	547231295	0	0
IndexIsCorrect_A	692081653	3514184	0	0
LockArbDecision_A	692081653	0	0	0
NoReadyValidNoGrant_A	692081653	0	0	0
ReadyAndValidImplyGrant_A	692081653	3514184	0	0
ReqAndReadyImplyGrant_A	692081653	3514184	0	0
ReqImpliesValid_A	692081653	3514184	0	0
ReqStaysHighUntilGranted0_M	692081653	0	0	0
RoundRobin_A	692081653	6	0	956
ValidKnown_A	692081653	547231295	0	0
gen_data_port_assertion.DataFlow_A	692081653	3514184	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	547231295	0	0
T1	839493	836330	0	0
T2	24417	24342	0	0
T3	278593	247300	0	0
T4	1146	1086	0	0
T5	1016781	900857	0	0
T6	1549	1499	0	0
T7	26608	24085	0	0
T8	584252	501206	0	0
T9	1053	955	0	0
T10	111611	72289	0	0
T11	35700	17836	0	0
T12	1234	504	0	0
T13	215680	107840	0	0
T14	97960	97422	0	0
T15	14797	14797	0	0
T16	0	221967	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	547231295	0	0
T1	839493	836330	0	0
T2	24417	24342	0	0
T3	278593	247300	0	0
T4	1146	1086	0	0
T5	1016781	900857	0	0
T6	1549	1499	0	0
T7	26608	24085	0	0
T8	584252	501206	0	0
T9	1053	955	0	0
T10	111611	72289	0	0
T11	35700	17836	0	0
T12	1234	504	0	0
T13	215680	107840	0	0
T14	97960	97422	0	0
T15	14797	14797	0	0
T16	0	221967	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	547231295	0	0
T1	839493	836330	0	0
T2	24417	24342	0	0
T3	278593	247300	0	0
T4	1146	1086	0	0
T5	1016781	900857	0	0
T6	1549	1499	0	0
T7	26608	24085	0	0
T8	584252	501206	0	0
T9	1053	955	0	0
T10	111611	72289	0	0
T11	35700	17836	0	0
T12	1234	504	0	0
T13	215680	107840	0	0
T14	97960	97422	0	0
T15	14797	14797	0	0
T16	0	221967	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	6	0	956
T24	0	1	0	0
T31	210156	1	0	1
T32	114340	0	0	1
T42	49165	0	0	1
T43	183315	0	0	1
T47	318900	0	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	54944	0	0	1
T60	15910	0	0	1
T61	38543	0	0	1
T62	204391	0	0	1
T63	9667	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	547231295	0	0
T1	839493	836330	0	0
T2	24417	24342	0	0
T3	278593	247300	0	0
T4	1146	1086	0	0
T5	1016781	900857	0	0
T6	1549	1499	0	0
T7	26608	24085	0	0
T8	584252	501206	0	0
T9	1053	955	0	0
T10	111611	72289	0	0
T11	35700	17836	0	0
T12	1234	504	0	0
T13	215680	107840	0	0
T14	97960	97422	0	0
T15	14797	14797	0	0
T16	0	221967	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	692081653	3514184	0	0
T1	839493	7906	0	0
T2	24417	832	0	0
T3	278593	1800	0	0
T4	1146	0	0	0
T5	1016781	7284	0	0
T6	1549	0	0	0
T7	26608	270	0	0
T8	584252	832	0	0
T9	1053	0	0	0
T10	111611	832	0	0
T11	35700	832	0	0
T12	1234	0	0	0
T13	215680	832	0	0
T14	97960	832	0	0
T15	14797	0	0	0
T16	0	2327	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1471	0	0
T31	0	4812	0	0
T32	0	5916	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	15867	0	0
T48	0	4649	0	0
T54	0	1106	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T5,T7
1	0	Covered	T3,T5,T7

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T7
1	0	Unreachable
1	1	Covered	T3,T5,T7

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T5,T7
0	0	1	Unreachable
0	0	0	Covered	T3,T5,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T3,T5,T7
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143494219	29256605	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	143494219	600511	0	0
GntImpliesValid_A	143494219	600511	0	0
GrantKnown_A	143494219	29256605	0	0
IdxKnown_A	143494219	29256605	0	0
IndexIsCorrect_A	143494219	600511	0	0
LockArbDecision_A	143494219	0	0	0
NoReadyValidNoGrant_A	143494219	0	0	0
ReadyAndValidImplyGrant_A	143494219	600511	0	0
ReqAndReadyImplyGrant_A	143494219	600511	0	0
ReqImpliesValid_A	143494219	600511	0	0
ReqStaysHighUntilGranted0_M	143494219	0	0	0
RoundRobin_A	143494219	0	0	0
ValidKnown_A	143494219	29256605	0	0
gen_data_port_assertion.DataFlow_A	143494219	600511	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	29256605	0	0
T3	30850	30488	0	0
T5	110522	105216	0	0
T7	2440	2440	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	504	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	62072	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	29256605	0	0
T3	30850	30488	0	0
T5	110522	105216	0	0
T7	2440	2440	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	504	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	62072	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	29256605	0	0
T3	30850	30488	0	0
T5	110522	105216	0	0
T7	2440	2440	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	504	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	62072	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	29256605	0	0
T3	30850	30488	0	0
T5	110522	105216	0	0
T7	2440	2440	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	504	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	62072	0	0
T27	0	178760	0	0
T28	0	1888	0	0
T29	0	79296	0	0
T31	0	188480	0	0
T32	0	182008	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	600511	0	0
T3	30850	1229	0	0
T5	110522	4858	0	0
T7	2440	206	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T14	97960	0	0	0
T15	14797	0	0	0
T16	0	2323	0	0
T27	0	3068	0	0
T28	0	197	0	0
T29	0	1336	0	0
T31	0	3468	0	0
T32	0	2339	0	0
T47	0	4295	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T16,T29

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T16,T29
1	0	Covered	T1,T16,T29

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T8
1	0	Unreachable
1	1	Covered	T1,T16,T29

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T16,T29
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T8

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T29
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	143494219	112969055	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	143494219	753999	0	0
GntImpliesValid_A	143494219	753999	0	0
GrantKnown_A	143494219	112969055	0	0
IdxKnown_A	143494219	112969055	0	0
IndexIsCorrect_A	143494219	753999	0	0
LockArbDecision_A	143494219	0	0	0
NoReadyValidNoGrant_A	143494219	0	0	0
ReadyAndValidImplyGrant_A	143494219	753999	0	0
ReqAndReadyImplyGrant_A	143494219	753999	0	0
ReqImpliesValid_A	143494219	753999	0	0
ReqStaysHighUntilGranted0_M	143494219	0	0	0
RoundRobin_A	143494219	0	0	0
ValidKnown_A	143494219	112969055	0	0
gen_data_port_assertion.DataFlow_A	143494219	753999	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	112969055	0	0
T1	571129	568058	0	0
T2	16540	16540	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	82990	0	0
T10	38433	37616	0	0
T11	17850	17836	0	0
T12	617	0	0	0
T13	107840	107840	0	0
T14	0	97422	0	0
T15	0	14797	0	0
T16	0	159895	0	0
T17	0	4256	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	112969055	0	0
T1	571129	568058	0	0
T2	16540	16540	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	82990	0	0
T10	38433	37616	0	0
T11	17850	17836	0	0
T12	617	0	0	0
T13	107840	107840	0	0
T14	0	97422	0	0
T15	0	14797	0	0
T16	0	159895	0	0
T17	0	4256	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	112969055	0	0
T1	571129	568058	0	0
T2	16540	16540	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	82990	0	0
T10	38433	37616	0	0
T11	17850	17836	0	0
T12	617	0	0	0
T13	107840	107840	0	0
T14	0	97422	0	0
T15	0	14797	0	0
T16	0	159895	0	0
T17	0	4256	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	112969055	0	0
T1	571129	568058	0	0
T2	16540	16540	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	82990	0	0
T10	38433	37616	0	0
T11	17850	17836	0	0
T12	617	0	0	0
T13	107840	107840	0	0
T14	0	97422	0	0
T15	0	14797	0	0
T16	0	159895	0	0
T17	0	4256	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	143494219	753999	0	0
T1	571129	1043	0	0
T2	16540	0	0	0
T3	30850	0	0	0
T5	110522	0	0	0
T7	2440	0	0	0
T8	82990	0	0	0
T10	38433	0	0	0
T11	17850	0	0	0
T12	617	0	0	0
T13	107840	0	0	0
T16	0	4	0	0
T29	0	135	0	0
T31	0	1344	0	0
T32	0	3577	0	0
T42	0	10	0	0
T43	0	2213	0	0
T47	0	11572	0	0
T48	0	4649	0	0
T54	0	1106	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T3

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	405093215	405005635	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	405093215	2159674	0	0
GntImpliesValid_A	405093215	2159674	0	0
GrantKnown_A	405093215	405005635	0	0
IdxKnown_A	405093215	405005635	0	0
IndexIsCorrect_A	405093215	2159674	0	0
LockArbDecision_A	405093215	0	0	0
NoReadyValidNoGrant_A	405093215	0	0	0
ReadyAndValidImplyGrant_A	405093215	2159674	0	0
ReqAndReadyImplyGrant_A	405093215	2159674	0	0
ReqImpliesValid_A	405093215	2159674	0	0
ReqStaysHighUntilGranted0_M	405093215	0	0	0
RoundRobin_A	405093215	6	0	956
ValidKnown_A	405093215	405005635	0	0
gen_data_port_assertion.DataFlow_A	405093215	2159674	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	405005635	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	405005635	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	405005635	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	6	0	956
T24	0	1	0	0
T31	210156	1	0	1
T32	114340	0	0	1
T42	49165	0	0	1
T43	183315	0	0	1
T47	318900	0	0	1
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	54944	0	0	1
T60	15910	0	0	1
T61	38543	0	0	1
T62	204391	0	0	1
T63	9667	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	405005635	0	0
T1	268364	268272	0	0
T2	7877	7802	0	0
T3	216893	216812	0	0
T4	1146	1086	0	0
T5	795737	795641	0	0
T6	1549	1499	0	0
T7	21728	21645	0	0
T8	418272	418216	0	0
T9	1053	955	0	0
T10	34745	34673	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	405093215	2159674	0	0
T1	268364	6863	0	0
T2	7877	832	0	0
T3	216893	571	0	0
T4	1146	0	0	0
T5	795737	2426	0	0
T6	1549	0	0	0
T7	21728	64	0	0
T8	418272	832	0	0
T9	1053	0	0	0
T10	34745	832	0	0
T11	0	832	0	0
T13	0	832	0	0
T14	0	832	0	0