Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
3451 | 
0 | 
0 | 
| T65 | 
5305 | 
1 | 
0 | 
0 | 
| T66 | 
8648 | 
3 | 
0 | 
0 | 
| T67 | 
13402 | 
8 | 
0 | 
0 | 
| T99 | 
24044 | 
247 | 
0 | 
0 | 
| T101 | 
10200 | 
1 | 
0 | 
0 | 
| T102 | 
23376 | 
341 | 
0 | 
0 | 
| T103 | 
82534 | 
4 | 
0 | 
0 | 
| T104 | 
2285 | 
6 | 
0 | 
0 | 
| T106 | 
2228 | 
102 | 
0 | 
0 | 
| T108 | 
14772 | 
110 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1757 | 
0 | 
0 | 
| T67 | 
13402 | 
19 | 
0 | 
0 | 
| T122 | 
8600 | 
5 | 
0 | 
0 | 
| T124 | 
36935 | 
245 | 
0 | 
0 | 
| T150 | 
35980 | 
45 | 
0 | 
0 | 
| T151 | 
6566 | 
28 | 
0 | 
0 | 
| T152 | 
5056 | 
10 | 
0 | 
0 | 
| T153 | 
6625 | 
1 | 
0 | 
0 | 
| T154 | 
33894 | 
36 | 
0 | 
0 | 
| T155 | 
91847 | 
79 | 
0 | 
0 | 
| T156 | 
34819 | 
45 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1544 | 
0 | 
0 | 
| T67 | 
13402 | 
23 | 
0 | 
0 | 
| T122 | 
8600 | 
14 | 
0 | 
0 | 
| T124 | 
36935 | 
200 | 
0 | 
0 | 
| T150 | 
35980 | 
42 | 
0 | 
0 | 
| T151 | 
6566 | 
7 | 
0 | 
0 | 
| T152 | 
5056 | 
11 | 
0 | 
0 | 
| T153 | 
6625 | 
9 | 
0 | 
0 | 
| T154 | 
33894 | 
37 | 
0 | 
0 | 
| T155 | 
91847 | 
82 | 
0 | 
0 | 
| T156 | 
34819 | 
24 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
2206 | 
0 | 
0 | 
| T67 | 
13402 | 
31 | 
0 | 
0 | 
| T122 | 
8600 | 
14 | 
0 | 
0 | 
| T124 | 
36935 | 
276 | 
0 | 
0 | 
| T150 | 
35980 | 
79 | 
0 | 
0 | 
| T151 | 
6566 | 
27 | 
0 | 
0 | 
| T152 | 
5056 | 
13 | 
0 | 
0 | 
| T153 | 
6625 | 
11 | 
0 | 
0 | 
| T154 | 
33894 | 
75 | 
0 | 
0 | 
| T155 | 
91847 | 
166 | 
0 | 
0 | 
| T156 | 
34819 | 
78 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
9504 | 
0 | 
0 | 
| T67 | 
13402 | 
197 | 
0 | 
0 | 
| T122 | 
8600 | 
128 | 
0 | 
0 | 
| T124 | 
36935 | 
247 | 
0 | 
0 | 
| T150 | 
35980 | 
635 | 
0 | 
0 | 
| T151 | 
6566 | 
41 | 
0 | 
0 | 
| T152 | 
5056 | 
4 | 
0 | 
0 | 
| T153 | 
6625 | 
36 | 
0 | 
0 | 
| T154 | 
33894 | 
752 | 
0 | 
0 | 
| T155 | 
91847 | 
644 | 
0 | 
0 | 
| T156 | 
34819 | 
400 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
8824 | 
0 | 
0 | 
| T67 | 
13402 | 
179 | 
0 | 
0 | 
| T122 | 
8600 | 
107 | 
0 | 
0 | 
| T124 | 
36935 | 
249 | 
0 | 
0 | 
| T150 | 
35980 | 
635 | 
0 | 
0 | 
| T151 | 
6566 | 
32 | 
0 | 
0 | 
| T152 | 
5056 | 
5 | 
0 | 
0 | 
| T153 | 
6625 | 
19 | 
0 | 
0 | 
| T154 | 
33894 | 
832 | 
0 | 
0 | 
| T155 | 
91847 | 
832 | 
0 | 
0 | 
| T156 | 
34819 | 
641 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
8850 | 
0 | 
0 | 
| T67 | 
13402 | 
47 | 
0 | 
0 | 
| T122 | 
8600 | 
226 | 
0 | 
0 | 
| T124 | 
36935 | 
212 | 
0 | 
0 | 
| T150 | 
35980 | 
806 | 
0 | 
0 | 
| T151 | 
6566 | 
42 | 
0 | 
0 | 
| T152 | 
5056 | 
123 | 
0 | 
0 | 
| T153 | 
6625 | 
25 | 
0 | 
0 | 
| T154 | 
33894 | 
663 | 
0 | 
0 | 
| T155 | 
91847 | 
591 | 
0 | 
0 | 
| T156 | 
34819 | 
553 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
9285 | 
0 | 
0 | 
| T67 | 
13402 | 
148 | 
0 | 
0 | 
| T122 | 
8600 | 
228 | 
0 | 
0 | 
| T124 | 
36935 | 
239 | 
0 | 
0 | 
| T128 | 
7244 | 
59 | 
0 | 
0 | 
| T150 | 
35980 | 
392 | 
0 | 
0 | 
| T152 | 
5056 | 
98 | 
0 | 
0 | 
| T153 | 
6625 | 
3 | 
0 | 
0 | 
| T154 | 
33894 | 
530 | 
0 | 
0 | 
| T155 | 
91847 | 
1356 | 
0 | 
0 | 
| T156 | 
34819 | 
879 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
8427 | 
0 | 
0 | 
| T67 | 
13402 | 
61 | 
0 | 
0 | 
| T122 | 
8600 | 
113 | 
0 | 
0 | 
| T124 | 
36935 | 
248 | 
0 | 
0 | 
| T150 | 
35980 | 
528 | 
0 | 
0 | 
| T151 | 
6566 | 
34 | 
0 | 
0 | 
| T152 | 
5056 | 
8 | 
0 | 
0 | 
| T153 | 
6625 | 
32 | 
0 | 
0 | 
| T154 | 
33894 | 
398 | 
0 | 
0 | 
| T155 | 
91847 | 
856 | 
0 | 
0 | 
| T156 | 
34819 | 
869 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
9238 | 
0 | 
0 | 
| T67 | 
13402 | 
92 | 
0 | 
0 | 
| T122 | 
8600 | 
211 | 
0 | 
0 | 
| T124 | 
36935 | 
235 | 
0 | 
0 | 
| T150 | 
35980 | 
357 | 
0 | 
0 | 
| T151 | 
6566 | 
19 | 
0 | 
0 | 
| T152 | 
5056 | 
139 | 
0 | 
0 | 
| T153 | 
6625 | 
13 | 
0 | 
0 | 
| T154 | 
33894 | 
823 | 
0 | 
0 | 
| T155 | 
91847 | 
860 | 
0 | 
0 | 
| T156 | 
34819 | 
661 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
8962 | 
0 | 
0 | 
| T67 | 
13402 | 
185 | 
0 | 
0 | 
| T122 | 
8600 | 
126 | 
0 | 
0 | 
| T124 | 
36935 | 
253 | 
0 | 
0 | 
| T150 | 
35980 | 
654 | 
0 | 
0 | 
| T151 | 
6566 | 
14 | 
0 | 
0 | 
| T152 | 
5056 | 
12 | 
0 | 
0 | 
| T153 | 
6625 | 
18 | 
0 | 
0 | 
| T154 | 
33894 | 
653 | 
0 | 
0 | 
| T155 | 
91847 | 
853 | 
0 | 
0 | 
| T156 | 
34819 | 
439 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
8796 | 
0 | 
0 | 
| T67 | 
13402 | 
81 | 
0 | 
0 | 
| T122 | 
8600 | 
9 | 
0 | 
0 | 
| T124 | 
36935 | 
286 | 
0 | 
0 | 
| T150 | 
35980 | 
667 | 
0 | 
0 | 
| T151 | 
6566 | 
20 | 
0 | 
0 | 
| T152 | 
5056 | 
10 | 
0 | 
0 | 
| T153 | 
6625 | 
46 | 
0 | 
0 | 
| T154 | 
33894 | 
464 | 
0 | 
0 | 
| T155 | 
91847 | 
1324 | 
0 | 
0 | 
| T156 | 
34819 | 
898 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4322 | 
0 | 
0 | 
| T67 | 
13402 | 
18 | 
0 | 
0 | 
| T122 | 
8600 | 
12 | 
0 | 
0 | 
| T124 | 
36935 | 
259 | 
0 | 
0 | 
| T126 | 
4539 | 
54 | 
0 | 
0 | 
| T150 | 
35980 | 
221 | 
0 | 
0 | 
| T152 | 
5056 | 
9 | 
0 | 
0 | 
| T153 | 
6625 | 
18 | 
0 | 
0 | 
| T154 | 
33894 | 
325 | 
0 | 
0 | 
| T155 | 
91847 | 
441 | 
0 | 
0 | 
| T156 | 
34819 | 
219 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4485 | 
0 | 
0 | 
| T67 | 
13402 | 
10 | 
0 | 
0 | 
| T122 | 
8600 | 
43 | 
0 | 
0 | 
| T124 | 
36935 | 
218 | 
0 | 
0 | 
| T150 | 
35980 | 
264 | 
0 | 
0 | 
| T151 | 
6566 | 
9 | 
0 | 
0 | 
| T152 | 
5056 | 
1 | 
0 | 
0 | 
| T153 | 
6625 | 
13 | 
0 | 
0 | 
| T154 | 
33894 | 
89 | 
0 | 
0 | 
| T155 | 
91847 | 
498 | 
0 | 
0 | 
| T156 | 
34819 | 
189 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4507 | 
0 | 
0 | 
| T67 | 
13402 | 
40 | 
0 | 
0 | 
| T122 | 
8600 | 
72 | 
0 | 
0 | 
| T124 | 
36935 | 
240 | 
0 | 
0 | 
| T150 | 
35980 | 
286 | 
0 | 
0 | 
| T151 | 
6566 | 
1 | 
0 | 
0 | 
| T152 | 
5056 | 
50 | 
0 | 
0 | 
| T153 | 
6625 | 
42 | 
0 | 
0 | 
| T154 | 
33894 | 
364 | 
0 | 
0 | 
| T155 | 
91847 | 
390 | 
0 | 
0 | 
| T156 | 
34819 | 
297 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4321 | 
0 | 
0 | 
| T67 | 
13402 | 
11 | 
0 | 
0 | 
| T122 | 
8600 | 
120 | 
0 | 
0 | 
| T124 | 
36935 | 
233 | 
0 | 
0 | 
| T126 | 
4539 | 
2 | 
0 | 
0 | 
| T150 | 
35980 | 
386 | 
0 | 
0 | 
| T152 | 
5056 | 
50 | 
0 | 
0 | 
| T153 | 
6625 | 
19 | 
0 | 
0 | 
| T154 | 
33894 | 
226 | 
0 | 
0 | 
| T155 | 
91847 | 
424 | 
0 | 
0 | 
| T156 | 
34819 | 
205 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4246 | 
0 | 
0 | 
| T67 | 
13402 | 
42 | 
0 | 
0 | 
| T122 | 
8600 | 
115 | 
0 | 
0 | 
| T124 | 
36935 | 
234 | 
0 | 
0 | 
| T150 | 
35980 | 
272 | 
0 | 
0 | 
| T151 | 
6566 | 
38 | 
0 | 
0 | 
| T152 | 
5056 | 
1 | 
0 | 
0 | 
| T153 | 
6625 | 
5 | 
0 | 
0 | 
| T154 | 
33894 | 
227 | 
0 | 
0 | 
| T155 | 
91847 | 
293 | 
0 | 
0 | 
| T156 | 
34819 | 
306 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4317 | 
0 | 
0 | 
| T67 | 
13402 | 
36 | 
0 | 
0 | 
| T122 | 
8600 | 
45 | 
0 | 
0 | 
| T124 | 
36935 | 
256 | 
0 | 
0 | 
| T150 | 
35980 | 
205 | 
0 | 
0 | 
| T151 | 
6566 | 
10 | 
0 | 
0 | 
| T152 | 
5056 | 
44 | 
0 | 
0 | 
| T153 | 
6625 | 
22 | 
0 | 
0 | 
| T154 | 
33894 | 
140 | 
0 | 
0 | 
| T155 | 
91847 | 
321 | 
0 | 
0 | 
| T156 | 
34819 | 
131 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4690 | 
0 | 
0 | 
| T67 | 
13402 | 
37 | 
0 | 
0 | 
| T122 | 
8600 | 
71 | 
0 | 
0 | 
| T124 | 
36935 | 
259 | 
0 | 
0 | 
| T150 | 
35980 | 
257 | 
0 | 
0 | 
| T151 | 
6566 | 
19 | 
0 | 
0 | 
| T152 | 
5056 | 
43 | 
0 | 
0 | 
| T153 | 
6625 | 
26 | 
0 | 
0 | 
| T154 | 
33894 | 
330 | 
0 | 
0 | 
| T155 | 
91847 | 
379 | 
0 | 
0 | 
| T156 | 
34819 | 
149 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4205 | 
0 | 
0 | 
| T67 | 
13402 | 
17 | 
0 | 
0 | 
| T122 | 
8600 | 
89 | 
0 | 
0 | 
| T124 | 
36935 | 
214 | 
0 | 
0 | 
| T150 | 
35980 | 
329 | 
0 | 
0 | 
| T151 | 
6566 | 
7 | 
0 | 
0 | 
| T152 | 
5056 | 
1 | 
0 | 
0 | 
| T153 | 
6625 | 
9 | 
0 | 
0 | 
| T154 | 
33894 | 
254 | 
0 | 
0 | 
| T155 | 
91847 | 
353 | 
0 | 
0 | 
| T156 | 
34819 | 
203 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4629 | 
0 | 
0 | 
| T67 | 
13402 | 
6 | 
0 | 
0 | 
| T102 | 
23376 | 
6 | 
0 | 
0 | 
| T122 | 
8600 | 
45 | 
0 | 
0 | 
| T124 | 
36935 | 
217 | 
0 | 
0 | 
| T150 | 
35980 | 
220 | 
0 | 
0 | 
| T151 | 
6566 | 
4 | 
0 | 
0 | 
| T152 | 
5056 | 
7 | 
0 | 
0 | 
| T153 | 
6625 | 
20 | 
0 | 
0 | 
| T154 | 
33894 | 
362 | 
0 | 
0 | 
| T155 | 
91847 | 
525 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4617 | 
0 | 
0 | 
| T67 | 
13402 | 
39 | 
0 | 
0 | 
| T122 | 
8600 | 
74 | 
0 | 
0 | 
| T124 | 
36935 | 
281 | 
0 | 
0 | 
| T150 | 
35980 | 
141 | 
0 | 
0 | 
| T151 | 
6566 | 
36 | 
0 | 
0 | 
| T152 | 
5056 | 
42 | 
0 | 
0 | 
| T153 | 
6625 | 
10 | 
0 | 
0 | 
| T154 | 
33894 | 
182 | 
0 | 
0 | 
| T155 | 
91847 | 
583 | 
0 | 
0 | 
| T156 | 
34819 | 
385 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4562 | 
0 | 
0 | 
| T67 | 
13402 | 
68 | 
0 | 
0 | 
| T122 | 
8600 | 
12 | 
0 | 
0 | 
| T124 | 
36935 | 
198 | 
0 | 
0 | 
| T150 | 
35980 | 
277 | 
0 | 
0 | 
| T151 | 
6566 | 
15 | 
0 | 
0 | 
| T152 | 
5056 | 
9 | 
0 | 
0 | 
| T153 | 
6625 | 
27 | 
0 | 
0 | 
| T154 | 
33894 | 
282 | 
0 | 
0 | 
| T155 | 
91847 | 
421 | 
0 | 
0 | 
| T156 | 
34819 | 
258 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4742 | 
0 | 
0 | 
| T67 | 
13402 | 
66 | 
0 | 
0 | 
| T99 | 
24044 | 
6 | 
0 | 
0 | 
| T122 | 
8600 | 
89 | 
0 | 
0 | 
| T124 | 
36935 | 
248 | 
0 | 
0 | 
| T150 | 
35980 | 
208 | 
0 | 
0 | 
| T151 | 
6566 | 
30 | 
0 | 
0 | 
| T152 | 
5056 | 
60 | 
0 | 
0 | 
| T153 | 
6625 | 
10 | 
0 | 
0 | 
| T154 | 
33894 | 
233 | 
0 | 
0 | 
| T155 | 
91847 | 
501 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4183 | 
0 | 
0 | 
| T67 | 
13402 | 
29 | 
0 | 
0 | 
| T124 | 
36935 | 
244 | 
0 | 
0 | 
| T126 | 
4539 | 
22 | 
0 | 
0 | 
| T150 | 
35980 | 
176 | 
0 | 
0 | 
| T151 | 
6566 | 
1 | 
0 | 
0 | 
| T152 | 
5056 | 
56 | 
0 | 
0 | 
| T153 | 
6625 | 
24 | 
0 | 
0 | 
| T154 | 
33894 | 
243 | 
0 | 
0 | 
| T155 | 
91847 | 
322 | 
0 | 
0 | 
| T156 | 
34819 | 
148 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4698 | 
0 | 
0 | 
| T67 | 
13402 | 
7 | 
0 | 
0 | 
| T122 | 
8600 | 
47 | 
0 | 
0 | 
| T124 | 
36935 | 
194 | 
0 | 
0 | 
| T150 | 
35980 | 
303 | 
0 | 
0 | 
| T151 | 
6566 | 
15 | 
0 | 
0 | 
| T152 | 
5056 | 
44 | 
0 | 
0 | 
| T153 | 
6625 | 
25 | 
0 | 
0 | 
| T154 | 
33894 | 
370 | 
0 | 
0 | 
| T155 | 
91847 | 
366 | 
0 | 
0 | 
| T156 | 
34819 | 
156 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4765 | 
0 | 
0 | 
| T67 | 
13402 | 
29 | 
0 | 
0 | 
| T122 | 
8600 | 
43 | 
0 | 
0 | 
| T124 | 
36935 | 
219 | 
0 | 
0 | 
| T150 | 
35980 | 
284 | 
0 | 
0 | 
| T151 | 
6566 | 
20 | 
0 | 
0 | 
| T152 | 
5056 | 
5 | 
0 | 
0 | 
| T153 | 
6625 | 
6 | 
0 | 
0 | 
| T154 | 
33894 | 
350 | 
0 | 
0 | 
| T155 | 
91847 | 
403 | 
0 | 
0 | 
| T156 | 
34819 | 
382 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4301 | 
0 | 
0 | 
| T67 | 
13402 | 
8 | 
0 | 
0 | 
| T122 | 
8600 | 
48 | 
0 | 
0 | 
| T124 | 
36935 | 
283 | 
0 | 
0 | 
| T126 | 
4539 | 
52 | 
0 | 
0 | 
| T150 | 
35980 | 
317 | 
0 | 
0 | 
| T152 | 
5056 | 
5 | 
0 | 
0 | 
| T153 | 
6625 | 
21 | 
0 | 
0 | 
| T154 | 
33894 | 
335 | 
0 | 
0 | 
| T155 | 
91847 | 
451 | 
0 | 
0 | 
| T156 | 
34819 | 
231 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
5049 | 
0 | 
0 | 
| T67 | 
13402 | 
96 | 
0 | 
0 | 
| T122 | 
8600 | 
103 | 
0 | 
0 | 
| T124 | 
36935 | 
251 | 
0 | 
0 | 
| T150 | 
35980 | 
371 | 
0 | 
0 | 
| T151 | 
6566 | 
14 | 
0 | 
0 | 
| T152 | 
5056 | 
11 | 
0 | 
0 | 
| T153 | 
6625 | 
7 | 
0 | 
0 | 
| T154 | 
33894 | 
220 | 
0 | 
0 | 
| T155 | 
91847 | 
384 | 
0 | 
0 | 
| T156 | 
34819 | 
309 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
5122 | 
0 | 
0 | 
| T67 | 
13402 | 
62 | 
0 | 
0 | 
| T99 | 
24044 | 
9 | 
0 | 
0 | 
| T122 | 
8600 | 
57 | 
0 | 
0 | 
| T124 | 
36935 | 
213 | 
0 | 
0 | 
| T150 | 
35980 | 
284 | 
0 | 
0 | 
| T151 | 
6566 | 
29 | 
0 | 
0 | 
| T152 | 
5056 | 
13 | 
0 | 
0 | 
| T153 | 
6625 | 
39 | 
0 | 
0 | 
| T154 | 
33894 | 
502 | 
0 | 
0 | 
| T155 | 
91847 | 
479 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4351 | 
0 | 
0 | 
| T67 | 
13402 | 
30 | 
0 | 
0 | 
| T99 | 
24044 | 
5 | 
0 | 
0 | 
| T122 | 
8600 | 
6 | 
0 | 
0 | 
| T124 | 
36935 | 
288 | 
0 | 
0 | 
| T150 | 
35980 | 
167 | 
0 | 
0 | 
| T151 | 
6566 | 
24 | 
0 | 
0 | 
| T152 | 
5056 | 
7 | 
0 | 
0 | 
| T153 | 
6625 | 
22 | 
0 | 
0 | 
| T154 | 
33894 | 
221 | 
0 | 
0 | 
| T155 | 
91847 | 
501 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4874 | 
0 | 
0 | 
| T67 | 
13402 | 
17 | 
0 | 
0 | 
| T122 | 
8600 | 
52 | 
0 | 
0 | 
| T124 | 
36935 | 
242 | 
0 | 
0 | 
| T126 | 
4539 | 
53 | 
0 | 
0 | 
| T150 | 
35980 | 
307 | 
0 | 
0 | 
| T151 | 
6566 | 
28 | 
0 | 
0 | 
| T152 | 
5056 | 
10 | 
0 | 
0 | 
| T154 | 
33894 | 
443 | 
0 | 
0 | 
| T155 | 
91847 | 
393 | 
0 | 
0 | 
| T156 | 
34819 | 
264 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4525 | 
0 | 
0 | 
| T67 | 
13402 | 
71 | 
0 | 
0 | 
| T122 | 
8600 | 
74 | 
0 | 
0 | 
| T124 | 
36935 | 
203 | 
0 | 
0 | 
| T150 | 
35980 | 
200 | 
0 | 
0 | 
| T151 | 
6566 | 
22 | 
0 | 
0 | 
| T152 | 
5056 | 
52 | 
0 | 
0 | 
| T153 | 
6625 | 
9 | 
0 | 
0 | 
| T154 | 
33894 | 
283 | 
0 | 
0 | 
| T155 | 
91847 | 
439 | 
0 | 
0 | 
| T156 | 
34819 | 
273 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4359 | 
0 | 
0 | 
| T67 | 
13402 | 
9 | 
0 | 
0 | 
| T124 | 
36935 | 
247 | 
0 | 
0 | 
| T126 | 
4539 | 
51 | 
0 | 
0 | 
| T128 | 
7244 | 
59 | 
0 | 
0 | 
| T150 | 
35980 | 
293 | 
0 | 
0 | 
| T151 | 
6566 | 
9 | 
0 | 
0 | 
| T152 | 
5056 | 
9 | 
0 | 
0 | 
| T154 | 
33894 | 
115 | 
0 | 
0 | 
| T155 | 
91847 | 
389 | 
0 | 
0 | 
| T156 | 
34819 | 
355 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4981 | 
0 | 
0 | 
| T67 | 
13402 | 
44 | 
0 | 
0 | 
| T122 | 
8600 | 
115 | 
0 | 
0 | 
| T124 | 
36935 | 
200 | 
0 | 
0 | 
| T150 | 
35980 | 
335 | 
0 | 
0 | 
| T151 | 
6566 | 
11 | 
0 | 
0 | 
| T152 | 
5056 | 
9 | 
0 | 
0 | 
| T153 | 
6625 | 
49 | 
0 | 
0 | 
| T154 | 
33894 | 
330 | 
0 | 
0 | 
| T155 | 
91847 | 
391 | 
0 | 
0 | 
| T156 | 
34819 | 
394 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4887 | 
0 | 
0 | 
| T67 | 
13402 | 
51 | 
0 | 
0 | 
| T122 | 
8600 | 
76 | 
0 | 
0 | 
| T124 | 
36935 | 
213 | 
0 | 
0 | 
| T150 | 
35980 | 
394 | 
0 | 
0 | 
| T151 | 
6566 | 
1 | 
0 | 
0 | 
| T152 | 
5056 | 
6 | 
0 | 
0 | 
| T153 | 
6625 | 
24 | 
0 | 
0 | 
| T154 | 
33894 | 
259 | 
0 | 
0 | 
| T155 | 
91847 | 
519 | 
0 | 
0 | 
| T156 | 
34819 | 
299 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1879 | 
0 | 
0 | 
| T67 | 
13402 | 
25 | 
0 | 
0 | 
| T122 | 
8600 | 
3 | 
0 | 
0 | 
| T124 | 
36935 | 
222 | 
0 | 
0 | 
| T150 | 
35980 | 
43 | 
0 | 
0 | 
| T151 | 
6566 | 
10 | 
0 | 
0 | 
| T152 | 
5056 | 
11 | 
0 | 
0 | 
| T153 | 
6625 | 
15 | 
0 | 
0 | 
| T154 | 
33894 | 
68 | 
0 | 
0 | 
| T155 | 
91847 | 
112 | 
0 | 
0 | 
| T156 | 
34819 | 
56 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1902 | 
0 | 
0 | 
| T67 | 
13402 | 
24 | 
0 | 
0 | 
| T122 | 
8600 | 
24 | 
0 | 
0 | 
| T124 | 
36935 | 
222 | 
0 | 
0 | 
| T150 | 
35980 | 
51 | 
0 | 
0 | 
| T151 | 
6566 | 
25 | 
0 | 
0 | 
| T152 | 
5056 | 
2 | 
0 | 
0 | 
| T153 | 
6625 | 
10 | 
0 | 
0 | 
| T154 | 
33894 | 
72 | 
0 | 
0 | 
| T155 | 
91847 | 
93 | 
0 | 
0 | 
| T156 | 
34819 | 
52 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1895 | 
0 | 
0 | 
| T67 | 
13402 | 
9 | 
0 | 
0 | 
| T122 | 
8600 | 
5 | 
0 | 
0 | 
| T124 | 
36935 | 
285 | 
0 | 
0 | 
| T150 | 
35980 | 
54 | 
0 | 
0 | 
| T151 | 
6566 | 
6 | 
0 | 
0 | 
| T152 | 
5056 | 
12 | 
0 | 
0 | 
| T153 | 
6625 | 
1 | 
0 | 
0 | 
| T154 | 
33894 | 
59 | 
0 | 
0 | 
| T155 | 
91847 | 
78 | 
0 | 
0 | 
| T156 | 
34819 | 
64 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1960 | 
0 | 
0 | 
| T67 | 
13402 | 
5 | 
0 | 
0 | 
| T122 | 
8600 | 
6 | 
0 | 
0 | 
| T124 | 
36935 | 
282 | 
0 | 
0 | 
| T150 | 
35980 | 
71 | 
0 | 
0 | 
| T151 | 
6566 | 
11 | 
0 | 
0 | 
| T152 | 
5056 | 
8 | 
0 | 
0 | 
| T153 | 
6625 | 
4 | 
0 | 
0 | 
| T154 | 
33894 | 
50 | 
0 | 
0 | 
| T155 | 
91847 | 
80 | 
0 | 
0 | 
| T156 | 
34819 | 
58 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
2362 | 
0 | 
0 | 
| T67 | 
13402 | 
17 | 
0 | 
0 | 
| T122 | 
8600 | 
28 | 
0 | 
0 | 
| T124 | 
36935 | 
285 | 
0 | 
0 | 
| T126 | 
4539 | 
2 | 
0 | 
0 | 
| T150 | 
35980 | 
94 | 
0 | 
0 | 
| T152 | 
5056 | 
16 | 
0 | 
0 | 
| T153 | 
6625 | 
21 | 
0 | 
0 | 
| T154 | 
33894 | 
72 | 
0 | 
0 | 
| T155 | 
91847 | 
135 | 
0 | 
0 | 
| T156 | 
34819 | 
67 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
4150 | 
0 | 
0 | 
| T23 | 
198054 | 
37 | 
0 | 
0 | 
| T33 | 
0 | 
4 | 
0 | 
0 | 
| T69 | 
1852 | 
0 | 
0 | 
0 | 
| T78 | 
0 | 
6 | 
0 | 
0 | 
| T96 | 
54824 | 
0 | 
0 | 
0 | 
| T129 | 
0 | 
30 | 
0 | 
0 | 
| T157 | 
0 | 
32 | 
0 | 
0 | 
| T158 | 
0 | 
39 | 
0 | 
0 | 
| T159 | 
0 | 
19 | 
0 | 
0 | 
| T160 | 
0 | 
78 | 
0 | 
0 | 
| T161 | 
0 | 
22 | 
0 | 
0 | 
| T162 | 
0 | 
23 | 
0 | 
0 | 
| T163 | 
32423 | 
0 | 
0 | 
0 | 
| T164 | 
266312 | 
0 | 
0 | 
0 | 
| T165 | 
999 | 
0 | 
0 | 
0 | 
| T166 | 
162730 | 
0 | 
0 | 
0 | 
| T167 | 
198045 | 
0 | 
0 | 
0 | 
| T168 | 
443271 | 
0 | 
0 | 
0 | 
| T169 | 
1169 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1921 | 
0 | 
0 | 
| T67 | 
13402 | 
10 | 
0 | 
0 | 
| T122 | 
8600 | 
10 | 
0 | 
0 | 
| T124 | 
36935 | 
220 | 
0 | 
0 | 
| T150 | 
35980 | 
61 | 
0 | 
0 | 
| T151 | 
6566 | 
21 | 
0 | 
0 | 
| T152 | 
5056 | 
10 | 
0 | 
0 | 
| T153 | 
6625 | 
10 | 
0 | 
0 | 
| T154 | 
33894 | 
47 | 
0 | 
0 | 
| T155 | 
91847 | 
77 | 
0 | 
0 | 
| T156 | 
34819 | 
43 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1959 | 
0 | 
0 | 
| T67 | 
13402 | 
12 | 
0 | 
0 | 
| T122 | 
8600 | 
13 | 
0 | 
0 | 
| T124 | 
36935 | 
184 | 
0 | 
0 | 
| T150 | 
35980 | 
70 | 
0 | 
0 | 
| T151 | 
6566 | 
10 | 
0 | 
0 | 
| T152 | 
5056 | 
13 | 
0 | 
0 | 
| T153 | 
6625 | 
19 | 
0 | 
0 | 
| T154 | 
33894 | 
75 | 
0 | 
0 | 
| T155 | 
91847 | 
101 | 
0 | 
0 | 
| T156 | 
34819 | 
45 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1647 | 
0 | 
0 | 
| T67 | 
13402 | 
13 | 
0 | 
0 | 
| T122 | 
8600 | 
1 | 
0 | 
0 | 
| T124 | 
36935 | 
294 | 
0 | 
0 | 
| T150 | 
35980 | 
30 | 
0 | 
0 | 
| T151 | 
6566 | 
29 | 
0 | 
0 | 
| T152 | 
5056 | 
10 | 
0 | 
0 | 
| T153 | 
6625 | 
25 | 
0 | 
0 | 
| T154 | 
33894 | 
28 | 
0 | 
0 | 
| T155 | 
91847 | 
81 | 
0 | 
0 | 
| T156 | 
34819 | 
43 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1639 | 
0 | 
0 | 
| T67 | 
13402 | 
6 | 
0 | 
0 | 
| T122 | 
8600 | 
9 | 
0 | 
0 | 
| T124 | 
36935 | 
252 | 
0 | 
0 | 
| T150 | 
35980 | 
32 | 
0 | 
0 | 
| T151 | 
6566 | 
11 | 
0 | 
0 | 
| T152 | 
5056 | 
4 | 
0 | 
0 | 
| T153 | 
6625 | 
7 | 
0 | 
0 | 
| T154 | 
33894 | 
32 | 
0 | 
0 | 
| T155 | 
91847 | 
68 | 
0 | 
0 | 
| T156 | 
34819 | 
43 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1632 | 
0 | 
0 | 
| T67 | 
13402 | 
10 | 
0 | 
0 | 
| T122 | 
8600 | 
12 | 
0 | 
0 | 
| T124 | 
36935 | 
262 | 
0 | 
0 | 
| T150 | 
35980 | 
34 | 
0 | 
0 | 
| T151 | 
6566 | 
12 | 
0 | 
0 | 
| T152 | 
5056 | 
10 | 
0 | 
0 | 
| T153 | 
6625 | 
2 | 
0 | 
0 | 
| T154 | 
33894 | 
14 | 
0 | 
0 | 
| T155 | 
91847 | 
66 | 
0 | 
0 | 
| T156 | 
34819 | 
42 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1667 | 
0 | 
0 | 
| T67 | 
13402 | 
3 | 
0 | 
0 | 
| T122 | 
8600 | 
12 | 
0 | 
0 | 
| T124 | 
36935 | 
235 | 
0 | 
0 | 
| T150 | 
35980 | 
29 | 
0 | 
0 | 
| T151 | 
6566 | 
13 | 
0 | 
0 | 
| T152 | 
5056 | 
5 | 
0 | 
0 | 
| T153 | 
6625 | 
27 | 
0 | 
0 | 
| T154 | 
33894 | 
32 | 
0 | 
0 | 
| T155 | 
91847 | 
78 | 
0 | 
0 | 
| T156 | 
34819 | 
37 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
2258 | 
0 | 
0 | 
| T67 | 
13402 | 
20 | 
0 | 
0 | 
| T122 | 
8600 | 
21 | 
0 | 
0 | 
| T124 | 
36935 | 
241 | 
0 | 
0 | 
| T150 | 
35980 | 
53 | 
0 | 
0 | 
| T151 | 
6566 | 
14 | 
0 | 
0 | 
| T152 | 
5056 | 
23 | 
0 | 
0 | 
| T153 | 
6625 | 
15 | 
0 | 
0 | 
| T154 | 
33894 | 
70 | 
0 | 
0 | 
| T155 | 
91847 | 
135 | 
0 | 
0 | 
| T156 | 
34819 | 
71 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1675 | 
0 | 
0 | 
| T67 | 
13402 | 
22 | 
0 | 
0 | 
| T122 | 
8600 | 
7 | 
0 | 
0 | 
| T124 | 
36935 | 
252 | 
0 | 
0 | 
| T150 | 
35980 | 
31 | 
0 | 
0 | 
| T151 | 
6566 | 
14 | 
0 | 
0 | 
| T152 | 
5056 | 
11 | 
0 | 
0 | 
| T153 | 
6625 | 
38 | 
0 | 
0 | 
| T154 | 
33894 | 
32 | 
0 | 
0 | 
| T155 | 
91847 | 
69 | 
0 | 
0 | 
| T156 | 
34819 | 
23 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
2629 | 
0 | 
0 | 
| T67 | 
13402 | 
17 | 
0 | 
0 | 
| T122 | 
8600 | 
15 | 
0 | 
0 | 
| T124 | 
36935 | 
246 | 
0 | 
0 | 
| T150 | 
35980 | 
126 | 
0 | 
0 | 
| T151 | 
6566 | 
12 | 
0 | 
0 | 
| T152 | 
5056 | 
5 | 
0 | 
0 | 
| T153 | 
6625 | 
30 | 
0 | 
0 | 
| T154 | 
33894 | 
127 | 
0 | 
0 | 
| T155 | 
91847 | 
185 | 
0 | 
0 | 
| T156 | 
34819 | 
104 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1926 | 
0 | 
0 | 
| T67 | 
13402 | 
16 | 
0 | 
0 | 
| T99 | 
24044 | 
2 | 
0 | 
0 | 
| T122 | 
8600 | 
14 | 
0 | 
0 | 
| T124 | 
36935 | 
266 | 
0 | 
0 | 
| T150 | 
35980 | 
53 | 
0 | 
0 | 
| T151 | 
6566 | 
27 | 
0 | 
0 | 
| T152 | 
5056 | 
13 | 
0 | 
0 | 
| T153 | 
6625 | 
11 | 
0 | 
0 | 
| T154 | 
33894 | 
42 | 
0 | 
0 | 
| T155 | 
91847 | 
81 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1771 | 
0 | 
0 | 
| T67 | 
13402 | 
18 | 
0 | 
0 | 
| T122 | 
8600 | 
9 | 
0 | 
0 | 
| T124 | 
36935 | 
266 | 
0 | 
0 | 
| T150 | 
35980 | 
40 | 
0 | 
0 | 
| T151 | 
6566 | 
50 | 
0 | 
0 | 
| T152 | 
5056 | 
4 | 
0 | 
0 | 
| T153 | 
6625 | 
7 | 
0 | 
0 | 
| T154 | 
33894 | 
39 | 
0 | 
0 | 
| T155 | 
91847 | 
73 | 
0 | 
0 | 
| T156 | 
34819 | 
31 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1693 | 
0 | 
0 | 
| T67 | 
13402 | 
7 | 
0 | 
0 | 
| T122 | 
8600 | 
7 | 
0 | 
0 | 
| T124 | 
36935 | 
236 | 
0 | 
0 | 
| T150 | 
35980 | 
25 | 
0 | 
0 | 
| T151 | 
6566 | 
42 | 
0 | 
0 | 
| T152 | 
5056 | 
15 | 
0 | 
0 | 
| T153 | 
6625 | 
17 | 
0 | 
0 | 
| T154 | 
33894 | 
51 | 
0 | 
0 | 
| T155 | 
91847 | 
44 | 
0 | 
0 | 
| T156 | 
34819 | 
37 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1607 | 
0 | 
0 | 
| T67 | 
13402 | 
4 | 
0 | 
0 | 
| T122 | 
8600 | 
8 | 
0 | 
0 | 
| T124 | 
36935 | 
243 | 
0 | 
0 | 
| T150 | 
35980 | 
30 | 
0 | 
0 | 
| T151 | 
6566 | 
29 | 
0 | 
0 | 
| T152 | 
5056 | 
11 | 
0 | 
0 | 
| T153 | 
6625 | 
42 | 
0 | 
0 | 
| T154 | 
33894 | 
28 | 
0 | 
0 | 
| T155 | 
91847 | 
34 | 
0 | 
0 | 
| T156 | 
34819 | 
24 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1631 | 
0 | 
0 | 
| T67 | 
13402 | 
23 | 
0 | 
0 | 
| T122 | 
8600 | 
10 | 
0 | 
0 | 
| T124 | 
36935 | 
218 | 
0 | 
0 | 
| T150 | 
35980 | 
32 | 
0 | 
0 | 
| T151 | 
6566 | 
31 | 
0 | 
0 | 
| T152 | 
5056 | 
6 | 
0 | 
0 | 
| T153 | 
6625 | 
16 | 
0 | 
0 | 
| T154 | 
33894 | 
34 | 
0 | 
0 | 
| T155 | 
91847 | 
56 | 
0 | 
0 | 
| T156 | 
34819 | 
39 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1619 | 
0 | 
0 | 
| T67 | 
13402 | 
11 | 
0 | 
0 | 
| T122 | 
8600 | 
7 | 
0 | 
0 | 
| T124 | 
36935 | 
241 | 
0 | 
0 | 
| T150 | 
35980 | 
43 | 
0 | 
0 | 
| T151 | 
6566 | 
26 | 
0 | 
0 | 
| T152 | 
5056 | 
9 | 
0 | 
0 | 
| T153 | 
6625 | 
35 | 
0 | 
0 | 
| T154 | 
33894 | 
29 | 
0 | 
0 | 
| T155 | 
91847 | 
67 | 
0 | 
0 | 
| T156 | 
34819 | 
25 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
407442214 | 
1658 | 
0 | 
0 | 
| T67 | 
13402 | 
9 | 
0 | 
0 | 
| T122 | 
8600 | 
8 | 
0 | 
0 | 
| T124 | 
36935 | 
243 | 
0 | 
0 | 
| T150 | 
35980 | 
37 | 
0 | 
0 | 
| T151 | 
6566 | 
20 | 
0 | 
0 | 
| T152 | 
5056 | 
17 | 
0 | 
0 | 
| T153 | 
6625 | 
17 | 
0 | 
0 | 
| T154 | 
33894 | 
33 | 
0 | 
0 | 
| T155 | 
91847 | 
77 | 
0 | 
0 | 
| T156 | 
34819 | 
46 | 
0 | 
0 |