Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3676920	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4250421

1

T1

1210

T2

18

T3

897

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4335003	1			T1	634		T2	1		T3	24
values[0x0]	1793862	1			T1	443		T2	11		T3	458
values[0x1]	1798476	1			T1	448		T2	11		T3	427

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2601293	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5326048

1

T1

1271

T2

21

T3

899

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30745	1			T1	14		T5	25		T6	64
valid_sources[0x01]	30307	1			T1	3		T4	2		T5	42
valid_sources[0x02]	29567	1			T1	6		T4	1		T5	9
valid_sources[0x03]	31906	1			T1	5		T4	1		T5	16
valid_sources[0x04]	29923	1			T1	8		T4	3		T5	18
valid_sources[0x05]	30796	1			T1	3		T5	18		T6	34
valid_sources[0x06]	30269	1			T1	6		T4	3		T5	37
valid_sources[0x07]	31736	1			T1	6		T4	1		T5	10
valid_sources[0x08]	28022	1			T1	7		T4	2		T5	36
valid_sources[0x09]	28664	1			T1	7		T4	8		T5	15
valid_sources[0x0a]	31721	1			T1	4		T4	6		T5	30
valid_sources[0x0b]	31327	1			T1	8		T4	3		T5	32
valid_sources[0x0c]	32565	1			T1	2		T5	21		T6	22
valid_sources[0x0d]	27917	1			T1	6		T4	4		T5	31
valid_sources[0x0e]	30413	1			T1	1		T3	1		T4	4
valid_sources[0x0f]	33550	1			T1	9		T4	5		T5	27
valid_sources[0x10]	28419	1			T1	8		T4	7		T5	36
valid_sources[0x11]	27393	1			T1	5		T5	39		T6	8
valid_sources[0x12]	29167	1			T1	5		T4	1		T5	28
valid_sources[0x13]	30316	1			T1	9		T4	6		T5	80
valid_sources[0x14]	30148	1			T1	5		T4	7		T5	13
valid_sources[0x15]	29962	1			T1	6		T4	7		T5	16
valid_sources[0x16]	31848	1			T1	5		T4	5		T5	42
valid_sources[0x17]	28711	1			T1	4		T5	19		T6	13
valid_sources[0x18]	47018	1			T1	6		T4	2		T5	29
valid_sources[0x19]	34298	1			T1	5		T4	3		T5	2
valid_sources[0x1a]	30084	1			T1	6		T5	12		T6	23
valid_sources[0x1b]	28520	1			T1	5		T4	1		T5	11
valid_sources[0x1c]	30230	1			T1	2		T3	490		T4	1
valid_sources[0x1d]	28777	1			T1	6		T4	2		T5	13
valid_sources[0x1e]	29046	1			T1	7		T4	4		T5	30
valid_sources[0x1f]	29012	1			T1	4		T4	4		T5	17
valid_sources[0x20]	31559	1			T1	6		T4	4		T5	9
valid_sources[0x21]	29991	1			T1	2		T4	11		T5	45
valid_sources[0x22]	34708	1			T1	4		T4	2		T5	17
valid_sources[0x23]	29376	1			T1	5		T3	1		T4	1
valid_sources[0x24]	33021	1			T1	7		T4	10		T5	38
valid_sources[0x25]	30240	1			T1	6		T4	3		T5	74
valid_sources[0x26]	34656	1			T1	5		T4	1		T5	48
valid_sources[0x27]	32693	1			T1	3		T4	2		T5	14
valid_sources[0x28]	29598	1			T1	9		T4	6		T5	34
valid_sources[0x29]	28552	1			T1	4		T4	3		T5	21
valid_sources[0x2a]	36863	1			T1	10		T4	2		T5	15
valid_sources[0x2b]	33738	1			T4	4		T5	16		T6	9
valid_sources[0x2c]	30921	1			T1	5		T4	8		T5	17
valid_sources[0x2d]	33485	1			T1	9		T4	5		T5	21
valid_sources[0x2e]	30993	1			T1	8		T4	6		T5	32
valid_sources[0x2f]	28987	1			T1	8		T4	2		T5	20
valid_sources[0x30]	29992	1			T1	3		T4	6		T5	10
valid_sources[0x31]	30868	1			T1	3		T4	1		T5	10
valid_sources[0x32]	27706	1			T1	9		T4	3		T5	5
valid_sources[0x33]	31769	1			T1	3		T4	2		T5	17
valid_sources[0x34]	33679	1			T1	5		T4	4		T5	13
valid_sources[0x35]	30162	1			T1	4		T2	3		T4	3
valid_sources[0x36]	30903	1			T1	4		T4	4		T5	20
valid_sources[0x37]	32462	1			T1	8		T4	2		T5	54
valid_sources[0x38]	30262	1			T1	5		T4	4		T5	34
valid_sources[0x39]	29300	1			T1	9		T4	2		T5	38
valid_sources[0x3a]	34170	1			T1	9		T4	5		T5	45
valid_sources[0x3b]	29068	1			T1	10		T4	12		T5	36
valid_sources[0x3c]	29672	1			T1	2		T4	2		T5	21
valid_sources[0x3d]	28783	1			T1	9		T4	3		T5	22
valid_sources[0x3e]	30482	1			T1	9		T4	4		T5	30
valid_sources[0x3f]	29866	1			T1	8		T4	9		T5	34
valid_sources[0x40]	31260	1			T1	13		T4	3		T5	14
valid_sources[0x41]	31762	1			T1	6		T4	1		T5	36
valid_sources[0x42]	32230	1			T1	13		T4	1		T5	7
valid_sources[0x43]	32959	1			T1	6		T4	5		T5	23
valid_sources[0x44]	33937	1			T1	5		T4	3		T5	11
valid_sources[0x45]	29712	1			T1	12		T5	26		T6	1
valid_sources[0x46]	30578	1			T1	7		T4	7		T5	10
valid_sources[0x47]	30811	1			T1	4		T4	5		T5	30
valid_sources[0x48]	30637	1			T1	7		T4	1		T5	17
valid_sources[0x49]	33796	1			T1	4		T4	6		T5	8
valid_sources[0x4a]	29989	1			T1	8		T4	4		T5	20
valid_sources[0x4b]	46114	1			T1	3		T4	3		T5	17
valid_sources[0x4c]	26934	1			T1	4		T5	53		T6	97
valid_sources[0x4d]	28576	1			T1	8		T4	5		T5	52
valid_sources[0x4e]	28955	1			T1	9		T4	2		T5	26
valid_sources[0x4f]	32838	1			T1	11		T5	35		T6	63
valid_sources[0x50]	30689	1			T1	7		T4	1		T5	31
valid_sources[0x51]	28224	1			T1	12		T4	2		T5	12
valid_sources[0x52]	27624	1			T1	4		T4	6		T5	14
valid_sources[0x53]	28316	1			T1	10		T4	1		T5	5
valid_sources[0x54]	30628	1			T1	5		T4	4		T5	12
valid_sources[0x55]	30386	1			T1	3		T4	5		T5	25
valid_sources[0x56]	34072	1			T1	5		T5	19		T6	48
valid_sources[0x57]	29520	1			T1	2		T4	8		T5	32
valid_sources[0x58]	28834	1			T1	3		T4	3		T5	59
valid_sources[0x59]	28906	1			T1	7		T4	1		T5	25
valid_sources[0x5a]	28724	1			T1	6		T4	13		T5	43
valid_sources[0x5b]	29854	1			T1	4		T4	2		T5	14
valid_sources[0x5c]	30204	1			T1	8		T4	12		T5	26
valid_sources[0x5d]	29586	1			T1	6		T4	4		T5	33
valid_sources[0x5e]	30666	1			T1	4		T4	3		T5	54
valid_sources[0x5f]	35641	1			T1	9		T2	1		T4	3
valid_sources[0x60]	30961	1			T1	6		T5	4		T6	25
valid_sources[0x61]	29314	1			T1	9		T4	3		T5	2
valid_sources[0x62]	33187	1			T1	6		T4	7		T5	57
valid_sources[0x63]	32414	1			T1	6		T3	416		T4	6
valid_sources[0x64]	29441	1			T1	5		T4	5		T5	9
valid_sources[0x65]	29768	1			T1	6		T3	1		T5	18
valid_sources[0x66]	30330	1			T1	5		T4	5		T5	9
valid_sources[0x67]	28514	1			T1	6		T4	4		T5	17
valid_sources[0x68]	28968	1			T1	2		T5	61		T6	4
valid_sources[0x69]	35396	1			T1	8		T4	3		T5	9
valid_sources[0x6a]	29809	1			T1	2		T4	5		T5	18
valid_sources[0x6b]	29225	1			T1	4		T4	6		T5	25
valid_sources[0x6c]	28759	1			T1	7		T4	1		T5	14
valid_sources[0x6d]	29288	1			T1	6		T2	7		T4	1
valid_sources[0x6e]	27987	1			T1	7		T4	4		T5	16
valid_sources[0x6f]	34304	1			T1	7		T4	3		T5	20
valid_sources[0x70]	28752	1			T1	9		T4	2		T5	7
valid_sources[0x71]	33767	1			T1	5		T5	15		T6	40
valid_sources[0x72]	28452	1			T1	5		T4	6		T5	44
valid_sources[0x73]	32319	1			T1	8		T5	22		T6	27
valid_sources[0x74]	29889	1			T1	6		T4	4		T5	22
valid_sources[0x75]	29944	1			T1	6		T4	8		T5	20
valid_sources[0x76]	31314	1			T1	8		T2	5		T5	28
valid_sources[0x77]	35447	1			T1	7		T4	10		T5	48
valid_sources[0x78]	33172	1			T1	5		T5	56		T6	9
valid_sources[0x79]	29725	1			T1	4		T4	3		T5	7
valid_sources[0x7a]	30896	1			T1	5		T4	8		T5	20
valid_sources[0x7b]	28988	1			T1	5		T4	2		T5	10
valid_sources[0x7c]	28965	1			T1	4		T4	3		T5	20
valid_sources[0x7d]	30745	1			T1	1		T4	4		T5	24
valid_sources[0x7e]	31294	1			T1	6		T4	5		T5	18
valid_sources[0x7f]	28550	1			T1	6		T4	11		T5	32
valid_sources[0x80]	27352	1			T1	7		T4	2		T5	30

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1000989

1

T1

325

T2

1

T3

14

values[0x0]

all_enables

biggest_size

1635398

1

T1

442

T2

9

T3

457

values[0x1]

all_enables

biggest_size

1614034

1

T1

443

T2

8

T3

426