Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3699854

1

T1

315

T2

5

T3

12

full_word

4251746

1

T1

1210

T2

18

T3

897

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	7951190	1			T1	1525		T2	23		T3	909
auto[TlIntgErrCmd]	133	1			T81	7		T108	9		T109	5
auto[TlIntgErrData]	137	1			T81	8		T108	11		T109	1
auto[TlIntgErrBoth]	140	1			T81	5		T108	10		T109	4

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4339640

1

T1

634

T2

1

T3

24

auto[1]

3611960

1

T1

891

T2

22

T3

885

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3338154	1			T1	309		T3	10		T5	2901
auto[TlIntgErrNone]	partial	auto[1]	361324	1			T1	6		T2	5		T3	2
auto[TlIntgErrNone]	full_word	auto[0]	1001306	1			T1	325		T2	1		T3	14
auto[TlIntgErrNone]	full_word	auto[1]	3250406	1			T1	885		T2	17		T3	883
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T81	3		T108	2		T109	4
auto[TlIntgErrCmd]	partial	auto[1]	64	1			T81	4		T108	5		T109	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T108	1		T173	1		T174	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T108	1		T173	1		T171	2
auto[TlIntgErrData]	partial	auto[0]	59	1			T81	6		T108	4		T109	1
auto[TlIntgErrData]	partial	auto[1]	64	1			T81	1		T108	6		T175	2
auto[TlIntgErrData]	full_word	auto[0]	9	1			T108	1		T172	1		T176	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T81	1		T175	1		T171	1
auto[TlIntgErrBoth]	partial	auto[0]	48	1			T81	2		T108	4		T109	1
auto[TlIntgErrBoth]	partial	auto[1]	82	1			T81	3		T108	6		T109	3
auto[TlIntgErrBoth]	full_word	auto[0]	1	1			T115	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T177	1		T115	1		T178	2