Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486376388	2865545	0	0
DepthKnown_A	486376388	486244015	0	0
RvalidKnown_A	486376388	486244015	0	0
WreadyKnown_A	486376388	486244015	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	2865545	0	0
T1	71991	1663	0	0
T2	4863	0	0	0
T3	22587	1663	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	0	0	0
T7	12687	0	0	0
T8	19888	0	0	0
T9	7055	1664	0	0
T10	413621	832	0	0
T11	0	7497	0	0
T13	0	1663	0	0
T14	0	13305	0	0
T15	0	2496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486376388	3337207	0	0
DepthKnown_A	486376388	486244015	0	0
RvalidKnown_A	486376388	486244015	0	0
WreadyKnown_A	486376388	486244015	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	3337207	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	3669	0	0
T6	427224	0	0	0
T7	12687	0	0	0
T8	19888	0	0	0
T9	7055	833	0	0
T10	413621	832	0	0
T11	0	7064	0	0
T13	0	832	0	0
T14	0	7488	0	0
T15	0	2496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486376388	179336	0	0
DepthKnown_A	486376388	486244015	0	0
RvalidKnown_A	486376388	486244015	0	0
WreadyKnown_A	486376388	486244015	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	179336	0	0
T6	427224	409	0	0
T7	12687	54	0	0
T8	19888	0	0	0
T9	7055	0	0	0
T10	413621	0	0	0
T11	361122	128	0	0
T12	1031	0	0	0
T14	0	64	0	0
T15	0	64	0	0
T16	0	728	0	0
T22	0	15	0	0
T27	8965	17	0	0
T28	486646	0	0	0
T31	0	1022	0	0
T44	0	288	0	0
T45	953	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486376388	439931	0	0
DepthKnown_A	486376388	486244015	0	0
RvalidKnown_A	486376388	486244015	0	0
WreadyKnown_A	486376388	486244015	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	439931	0	0
T6	427224	409	0	0
T7	12687	54	0	0
T8	19888	0	0	0
T9	7055	0	0	0
T10	413621	0	0	0
T11	361122	581	0	0
T12	1031	0	0	0
T14	0	64	0	0
T15	0	64	0	0
T16	0	727	0	0
T22	0	15	0	0
T27	8965	66	0	0
T28	486646	0	0	0
T31	0	4703	0	0
T44	0	288	0	0
T45	953	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486376388	6348486	0	0
DepthKnown_A	486376388	486244015	0	0
RvalidKnown_A	486376388	486244015	0	0
WreadyKnown_A	486376388	486244015	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	6348486	0	0
T1	71991	693	0	0
T2	4863	23	0	0
T3	22587	77	0	0
T4	321724	63	0	0
T5	162923	5915	0	0
T6	427224	6613	0	0
T7	12687	1026	0	0
T8	19888	121	0	0
T9	7055	139	0	0
T10	413621	723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	486376388	15002693	0	0
DepthKnown_A	486376388	486244015	0	0
RvalidKnown_A	486376388	486244015	0	0
WreadyKnown_A	486376388	486244015	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	15002693	0	0
T1	71991	693	0	0
T2	4863	23	0	0
T3	22587	77	0	0
T4	321724	63	0	0
T5	162923	25214	0	0
T6	427224	6603	0	0
T7	12687	1026	0	0
T8	19888	121	0	0
T9	7055	679	0	0
T10	413621	723	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	486376388	486244015	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0