Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T27
1	0	Covered	T6,T7,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Unreachable
1	1	Covered	T6,T7,T27

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T11,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T27

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T27
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	784399229	633010816	0	0
CheckNGreaterZero_A	2868	2868	0	0
GntImpliesReady_A	784399229	3621291	0	0
GntImpliesValid_A	784399229	3621291	0	0
GrantKnown_A	784399229	633010816	0	0
IdxKnown_A	784399229	633010816	0	0
IndexIsCorrect_A	784399229	3621291	0	0
LockArbDecision_A	784399229	0	0	0
NoReadyValidNoGrant_A	784399229	0	0	0
ReadyAndValidImplyGrant_A	784399229	3621291	0	0
ReqAndReadyImplyGrant_A	784399229	3621291	0	0
ReqImpliesValid_A	784399229	3621291	0	0
ReqStaysHighUntilGranted0_M	784399229	0	0	0
RoundRobin_A	784399229	7	0	956
ValidKnown_A	784399229	633010816	0	0
gen_data_port_assertion.DataFlow_A	784399229	3621291	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	633010816	0	0
T1	85790	85697	0	0
T2	6419	5292	0	0
T3	29739	25970	0	0
T4	427664	374413	0	0
T5	206315	184551	0	0
T6	533348	478275	0	0
T7	19647	16080	0	0
T8	112114	63412	0	0
T9	20579	13731	0	0
T10	548983	481207	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2868	2868	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	633010816	0	0
T1	85790	85697	0	0
T2	6419	5292	0	0
T3	29739	25970	0	0
T4	427664	374413	0	0
T5	206315	184551	0	0
T6	533348	478275	0	0
T7	19647	16080	0	0
T8	112114	63412	0	0
T9	20579	13731	0	0
T10	548983	481207	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	633010816	0	0
T1	85790	85697	0	0
T2	6419	5292	0	0
T3	29739	25970	0	0
T4	427664	374413	0	0
T5	206315	184551	0	0
T6	533348	478275	0	0
T7	19647	16080	0	0
T8	112114	63412	0	0
T9	20579	13731	0	0
T10	548983	481207	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	7	0	956
T34	236114	1	0	1
T35	4250	0	0	1
T43	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	5650	0	0	1
T68	842	0	0	1
T69	532992	0	0	1
T70	246208	0	0	1
T71	623250	0	0	1
T72	135598	0	0	1
T73	368999	0	0	1
T74	17133	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	633010816	0	0
T1	85790	85697	0	0
T2	6419	5292	0	0
T3	29739	25970	0	0
T4	427664	374413	0	0
T5	206315	184551	0	0
T6	533348	478275	0	0
T7	19647	16080	0	0
T8	112114	63412	0	0
T9	20579	13731	0	0
T10	548983	481207	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	784399229	3621291	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	480286	3257	0	0
T7	16167	347	0	0
T8	66001	0	0	0
T9	13817	832	0	0
T10	481302	832	0	0
T11	655058	4812	0	0
T13	102344	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	4599	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	186	0	0
T28	122984	0	0	0
T29	145700	0	0	0
T30	35378	0	0	0
T31	562362	7089	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T59	0	6613	0	0
T60	0	138	0	0
T61	0	3422	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T27
1	0	Covered	T6,T7,T27

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T7
1	0	Unreachable
1	1	Covered	T6,T7,T27

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T6,T7,T27
0	0	1	Unreachable
0	0	0	Covered	T2,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T27
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149972786	27635627	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149972786	585844	0	0
GntImpliesValid_A	149972786	585844	0	0
GrantKnown_A	149972786	27635627	0	0
IdxKnown_A	149972786	27635627	0	0
IndexIsCorrect_A	149972786	585844	0	0
LockArbDecision_A	149972786	0	0	0
NoReadyValidNoGrant_A	149972786	0	0	0
ReadyAndValidImplyGrant_A	149972786	585844	0	0
ReqAndReadyImplyGrant_A	149972786	585844	0	0
ReqImpliesValid_A	149972786	585844	0	0
ReqStaysHighUntilGranted0_M	149972786	0	0	0
RoundRobin_A	149972786	0	0	0
ValidKnown_A	149972786	27635627	0	0
gen_data_port_assertion.DataFlow_A	149972786	585844	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	27635627	0	0
T2	778	504	0	0
T3	3576	0	0	0
T4	52970	0	0	0
T5	21696	0	0	0
T6	53062	51128	0	0
T7	3480	3480	0	0
T8	46113	43584	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	27635627	0	0
T2	778	504	0	0
T3	3576	0	0	0
T4	52970	0	0	0
T5	21696	0	0	0
T6	53062	51128	0	0
T7	3480	3480	0	0
T8	46113	43584	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	27635627	0	0
T2	778	504	0	0
T3	3576	0	0	0
T4	52970	0	0	0
T5	21696	0	0	0
T6	53062	51128	0	0
T7	3480	3480	0	0
T8	46113	43584	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	27635627	0	0
T2	778	504	0	0
T3	3576	0	0	0
T4	52970	0	0	0
T5	21696	0	0	0
T6	53062	51128	0	0
T7	3480	3480	0	0
T8	46113	43584	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T27	3678	3240	0	0
T28	0	116792	0	0
T29	0	69736	0	0
T30	0	33672	0	0
T31	0	81640	0	0
T32	0	936	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	585844	0	0
T6	53062	2244	0	0
T7	3480	254	0	0
T8	46113	0	0	0
T9	6762	0	0	0
T10	67681	0	0	0
T11	327529	0	0	0
T13	51172	0	0	0
T16	0	1489	0	0
T22	0	71	0	0
T23	0	19	0	0
T25	0	2759	0	0
T27	3678	122	0	0
T28	122984	0	0	0
T29	72850	0	0	0
T31	0	4042	0	0
T59	0	2560	0	0
T60	0	138	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T14,T15

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T14,T15
1	0	Covered	T11,T14,T15

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T11,T14,T15

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T14,T15
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T14,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	149972786	121007914	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	149972786	803484	0	0
GntImpliesValid_A	149972786	803484	0	0
GrantKnown_A	149972786	121007914	0	0
IdxKnown_A	149972786	121007914	0	0
IndexIsCorrect_A	149972786	803484	0	0
LockArbDecision_A	149972786	0	0	0
NoReadyValidNoGrant_A	149972786	0	0	0
ReadyAndValidImplyGrant_A	149972786	803484	0	0
ReqAndReadyImplyGrant_A	149972786	803484	0	0
ReqImpliesValid_A	149972786	803484	0	0
ReqStaysHighUntilGranted0_M	149972786	0	0	0
RoundRobin_A	149972786	0	0	0
ValidKnown_A	149972786	121007914	0	0
gen_data_port_assertion.DataFlow_A	149972786	803484	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	121007914	0	0
T1	13799	13799	0	0
T2	778	0	0	0
T3	3576	3458	0	0
T4	52970	52766	0	0
T5	21696	21696	0	0
T6	53062	0	0	0
T7	3480	0	0	0
T8	46113	0	0	0
T9	6762	6762	0	0
T10	67681	67681	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	121007914	0	0
T1	13799	13799	0	0
T2	778	0	0	0
T3	3576	3458	0	0
T4	52970	52766	0	0
T5	21696	21696	0	0
T6	53062	0	0	0
T7	3480	0	0	0
T8	46113	0	0	0
T9	6762	6762	0	0
T10	67681	67681	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	121007914	0	0
T1	13799	13799	0	0
T2	778	0	0	0
T3	3576	3458	0	0
T4	52970	52766	0	0
T5	21696	21696	0	0
T6	53062	0	0	0
T7	3480	0	0	0
T8	46113	0	0	0
T9	6762	6762	0	0
T10	67681	67681	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	121007914	0	0
T1	13799	13799	0	0
T2	778	0	0	0
T3	3576	3458	0	0
T4	52970	52766	0	0
T5	21696	21696	0	0
T6	53062	0	0	0
T7	3480	0	0	0
T8	46113	0	0	0
T9	6762	6762	0	0
T10	67681	67681	0	0
T11	0	326359	0	0
T13	0	50496	0	0
T14	0	337170	0	0
T15	0	208124	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	149972786	803484	0	0
T11	327529	518	0	0
T13	51172	0	0	0
T14	338401	296	0	0
T15	209264	2176	0	0
T16	0	3110	0	0
T18	0	6185	0	0
T29	72850	0	0	0
T30	35378	0	0	0
T31	562362	3047	0	0
T32	936	0	0	0
T44	253656	1682	0	0
T50	0	3453	0	0
T58	8304	0	0	0
T59	0	4053	0	0
T61	0	3422	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T7,T27

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T27
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T7,T27
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	484453657	484367275	0	0
CheckNGreaterZero_A	956	956	0	0
GntImpliesReady_A	484453657	2231963	0	0
GntImpliesValid_A	484453657	2231963	0	0
GrantKnown_A	484453657	484367275	0	0
IdxKnown_A	484453657	484367275	0	0
IndexIsCorrect_A	484453657	2231963	0	0
LockArbDecision_A	484453657	0	0	0
NoReadyValidNoGrant_A	484453657	0	0	0
ReadyAndValidImplyGrant_A	484453657	2231963	0	0
ReqAndReadyImplyGrant_A	484453657	2231963	0	0
ReqImpliesValid_A	484453657	2231963	0	0
ReqStaysHighUntilGranted0_M	484453657	0	0	0
RoundRobin_A	484453657	7	0	956
ValidKnown_A	484453657	484367275	0	0
gen_data_port_assertion.DataFlow_A	484453657	2231963	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	484367275	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	956	956	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	484367275	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	484367275	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	7	0	956
T34	236114	1	0	1
T35	4250	0	0	1
T43	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	5650	0	0	1
T68	842	0	0	1
T69	532992	0	0	1
T70	246208	0	0	1
T71	623250	0	0	1
T72	135598	0	0	1
T73	368999	0	0	1
T74	17133	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	484367275	0	0
T1	71991	71898	0	0
T2	4863	4788	0	0
T3	22587	22512	0	0
T4	321724	321647	0	0
T5	162923	162855	0	0
T6	427224	427147	0	0
T7	12687	12600	0	0
T8	19888	19828	0	0
T9	7055	6969	0	0
T10	413621	413526	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	484453657	2231963	0	0
T1	71991	832	0	0
T2	4863	0	0	0
T3	22587	832	0	0
T4	321724	832	0	0
T5	162923	832	0	0
T6	427224	1013	0	0
T7	12687	93	0	0
T8	19888	0	0	0
T9	7055	832	0	0
T10	413621	832	0	0
T11	0	4294	0	0
T27	0	64	0	0