Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3854497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4428343

1

T1

4

T2

80

T3

887

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4573776	1			T1	1		T2	184		T3	2
values[0x0]	1856408	1			T1	14		T2	37		T3	451
values[0x1]	1852656	1			T1	12		T2	33		T3	437

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2730225	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5552615

1

T1

5

T2

130

T3

889

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28847	1			T3	6		T4	12		T7	18
valid_sources[0x01]	32774	1			T3	6		T4	8		T5	1
valid_sources[0x02]	33961	1			T2	3		T3	3		T4	10
valid_sources[0x03]	37065	1			T2	2		T4	3		T7	20
valid_sources[0x04]	31114	1			T4	10		T7	30		T8	4
valid_sources[0x05]	28038	1			T4	5		T5	1		T7	31
valid_sources[0x06]	29865	1			T2	2		T4	12		T7	24
valid_sources[0x07]	32753	1			T2	3		T3	15		T4	3
valid_sources[0x08]	29942	1			T2	3		T3	1		T4	3
valid_sources[0x09]	29360	1			T2	2		T3	11		T4	4
valid_sources[0x0a]	37142	1			T4	3		T7	27		T8	3
valid_sources[0x0b]	33671	1			T3	7		T4	6		T7	23
valid_sources[0x0c]	29777	1			T4	4		T7	19		T8	1
valid_sources[0x0d]	31958	1			T2	4		T3	7		T4	8
valid_sources[0x0e]	30521	1			T2	1		T3	3		T4	10
valid_sources[0x0f]	36215	1			T2	3		T3	7		T4	6
valid_sources[0x10]	32193	1			T1	1		T3	6		T4	10
valid_sources[0x11]	31387	1			T3	1		T4	6		T5	12
valid_sources[0x12]	31072	1			T3	1		T4	4		T7	44
valid_sources[0x13]	30136	1			T3	1		T4	9		T7	29
valid_sources[0x14]	32602	1			T2	2		T3	12		T4	6
valid_sources[0x15]	31900	1			T3	3		T4	1		T5	25
valid_sources[0x16]	30092	1			T2	1		T4	8		T6	3
valid_sources[0x17]	30653	1			T2	5		T3	6		T4	7
valid_sources[0x18]	28254	1			T4	14		T7	21		T8	2
valid_sources[0x19]	31455	1			T3	2		T4	6		T7	26
valid_sources[0x1a]	30821	1			T4	4		T7	17		T8	1
valid_sources[0x1b]	30203	1			T3	5		T4	5		T7	34
valid_sources[0x1c]	30454	1			T3	6		T4	12		T5	1
valid_sources[0x1d]	36988	1			T3	7		T4	4		T7	33
valid_sources[0x1e]	29819	1			T2	3		T3	4		T4	3
valid_sources[0x1f]	29842	1			T3	3		T4	8		T7	22
valid_sources[0x20]	30702	1			T2	2		T3	2		T4	2
valid_sources[0x21]	29917	1			T2	4		T3	7		T4	7
valid_sources[0x22]	32335	1			T3	2		T4	5		T7	25
valid_sources[0x23]	36206	1			T2	3		T3	1		T4	12
valid_sources[0x24]	28542	1			T2	2		T3	2		T4	6
valid_sources[0x25]	32559	1			T2	7		T3	4		T4	10
valid_sources[0x26]	32048	1			T3	7		T4	5		T6	1
valid_sources[0x27]	32673	1			T2	6		T3	1		T4	10
valid_sources[0x28]	30596	1			T2	1		T4	10		T7	42
valid_sources[0x29]	35451	1			T4	6		T7	47		T8	7
valid_sources[0x2a]	29191	1			T2	5		T3	6		T4	5
valid_sources[0x2b]	32145	1			T3	5		T4	7		T7	18
valid_sources[0x2c]	31476	1			T2	3		T3	9		T4	9
valid_sources[0x2d]	30116	1			T2	2		T3	2		T4	3
valid_sources[0x2e]	32272	1			T1	3		T3	14		T4	4
valid_sources[0x2f]	34271	1			T2	3		T4	8		T7	28
valid_sources[0x30]	38332	1			T4	5		T7	27		T8	3
valid_sources[0x31]	30586	1			T4	5		T7	35		T8	5
valid_sources[0x32]	28019	1			T3	1		T4	4		T6	1
valid_sources[0x33]	29355	1			T2	9		T3	5		T4	11
valid_sources[0x34]	30626	1			T3	2		T4	6		T7	24
valid_sources[0x35]	33260	1			T4	14		T7	48		T9	2
valid_sources[0x36]	30229	1			T3	3		T4	3		T6	2
valid_sources[0x37]	30538	1			T2	1		T3	2		T4	7
valid_sources[0x38]	32012	1			T3	4		T4	6		T7	22
valid_sources[0x39]	32336	1			T3	1		T4	3		T7	33
valid_sources[0x3a]	31537	1			T3	4		T4	8		T7	52
valid_sources[0x3b]	39977	1			T3	1		T4	7		T6	1
valid_sources[0x3c]	34463	1			T3	2		T4	6		T7	21
valid_sources[0x3d]	37958	1			T4	9		T6	1		T7	25
valid_sources[0x3e]	28010	1			T3	16		T4	5		T7	33
valid_sources[0x3f]	30365	1			T3	3		T4	10		T7	35
valid_sources[0x40]	34620	1			T3	3		T4	13		T7	25
valid_sources[0x41]	30144	1			T2	1		T4	6		T6	1
valid_sources[0x42]	30400	1			T2	2		T3	4		T4	6
valid_sources[0x43]	49734	1			T1	1		T3	2		T4	6
valid_sources[0x44]	31416	1			T3	10		T4	9		T6	2
valid_sources[0x45]	30641	1			T2	2		T4	8		T6	2
valid_sources[0x46]	30172	1			T4	9		T7	28		T8	12
valid_sources[0x47]	31389	1			T3	2		T4	10		T7	25
valid_sources[0x48]	34956	1			T4	8		T6	1		T7	36
valid_sources[0x49]	43942	1			T2	4		T3	7		T4	8
valid_sources[0x4a]	34466	1			T2	2		T3	4		T4	10
valid_sources[0x4b]	30845	1			T3	4		T4	8		T6	2
valid_sources[0x4c]	33716	1			T2	2		T4	4		T7	26
valid_sources[0x4d]	29921	1			T2	1		T3	2		T4	8
valid_sources[0x4e]	30460	1			T3	1		T4	6		T6	1
valid_sources[0x4f]	29813	1			T4	5		T5	1		T6	1
valid_sources[0x50]	28558	1			T2	3		T3	1		T4	5
valid_sources[0x51]	32956	1			T4	3		T7	30		T8	1
valid_sources[0x52]	33110	1			T2	2		T4	5		T7	56
valid_sources[0x53]	33295	1			T3	6		T4	10		T6	1
valid_sources[0x54]	34771	1			T2	6		T3	2		T4	5
valid_sources[0x55]	30726	1			T3	9		T4	5		T7	30
valid_sources[0x56]	35862	1			T3	2		T4	8		T5	31
valid_sources[0x57]	30491	1			T3	3		T4	6		T7	28
valid_sources[0x58]	31178	1			T3	6		T4	3		T7	19
valid_sources[0x59]	29738	1			T3	6		T4	4		T7	34
valid_sources[0x5a]	70764	1			T2	1		T3	4		T4	5
valid_sources[0x5b]	35403	1			T4	6		T7	28		T10	3
valid_sources[0x5c]	29416	1			T3	3		T4	5		T5	1
valid_sources[0x5d]	32904	1			T2	7		T3	4		T4	4
valid_sources[0x5e]	29241	1			T4	12		T6	1		T7	30
valid_sources[0x5f]	30680	1			T2	7		T4	7		T7	34
valid_sources[0x60]	34003	1			T3	11		T4	8		T7	20
valid_sources[0x61]	33971	1			T2	2		T3	1		T4	7
valid_sources[0x62]	35178	1			T2	1		T3	7		T4	4
valid_sources[0x63]	29635	1			T2	5		T4	10		T6	1
valid_sources[0x64]	32544	1			T1	1		T2	1		T3	3
valid_sources[0x65]	30122	1			T2	1		T4	7		T6	1
valid_sources[0x66]	30997	1			T4	8		T5	5		T7	18
valid_sources[0x67]	29273	1			T3	2		T4	8		T6	1
valid_sources[0x68]	30864	1			T4	6		T7	47		T8	10
valid_sources[0x69]	31244	1			T3	4		T4	10		T7	29
valid_sources[0x6a]	45448	1			T2	3		T3	4		T4	7
valid_sources[0x6b]	33691	1			T4	3		T7	39		T8	10
valid_sources[0x6c]	32519	1			T4	9		T6	2		T7	31
valid_sources[0x6d]	34152	1			T2	2		T3	8		T4	6
valid_sources[0x6e]	32852	1			T3	7		T4	5		T5	2
valid_sources[0x6f]	31019	1			T2	1		T3	1		T4	9
valid_sources[0x70]	31767	1			T3	7		T4	5		T6	2
valid_sources[0x71]	45714	1			T2	2		T4	9		T7	25
valid_sources[0x72]	31156	1			T2	4		T3	15		T4	10
valid_sources[0x73]	32391	1			T3	2		T4	12		T7	36
valid_sources[0x74]	30790	1			T3	2		T4	6		T6	3
valid_sources[0x75]	49944	1			T2	2		T3	4		T4	8
valid_sources[0x76]	34286	1			T2	3		T3	5		T4	3
valid_sources[0x77]	35332	1			T1	3		T2	1		T3	7
valid_sources[0x78]	28867	1			T2	1		T3	2		T4	6
valid_sources[0x79]	31775	1			T1	1		T3	3		T4	7
valid_sources[0x7a]	30317	1			T2	11		T3	5		T4	8
valid_sources[0x7b]	31254	1			T3	1		T4	8		T5	8
valid_sources[0x7c]	31543	1			T1	3		T3	4		T4	6
valid_sources[0x7d]	32370	1			T3	4		T4	6		T7	42
valid_sources[0x7e]	30162	1			T3	14		T4	6		T7	41
valid_sources[0x7f]	33075	1			T4	7		T7	16		T8	6
valid_sources[0x80]	33662	1			T2	1		T4	5		T7	24

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1076166

1

T2

35

T3

2

T4

49

values[0x0]

all_enables

biggest_size

1690264

1

T1

4

T2

29

T3

450

values[0x1]

all_enables

biggest_size

1661913

1

T2

16

T3

435

T4

16