Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3880226

1

T1

23

T2

174

T3

3

full_word

4429925

1

T1

4

T2

80

T3

887

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8309751	1			T1	27		T2	254		T3	890
auto[TlIntgErrCmd]	133	1			T50	11		T87	8		T88	3
auto[TlIntgErrData]	136	1			T50	14		T87	5		T88	6
auto[TlIntgErrBoth]	131	1			T50	5		T87	7		T88	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4579956

1

T1

1

T2

184

T3

2

auto[1]

3730195

1

T1

26

T2

70

T3

888

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3503141	1			T1	1		T2	149		T4	1680
auto[TlIntgErrNone]	partial	auto[1]	376716	1			T1	22		T2	25		T3	3
auto[TlIntgErrNone]	full_word	auto[0]	1076636	1			T2	35		T3	2		T4	49
auto[TlIntgErrNone]	full_word	auto[1]	3353258	1			T1	4		T2	45		T3	885
auto[TlIntgErrCmd]	partial	auto[0]	47	1			T50	8		T87	3		T88	1
auto[TlIntgErrCmd]	partial	auto[1]	78	1			T50	3		T87	5		T88	2
auto[TlIntgErrCmd]	full_word	auto[0]	5	1			T139	1		T104	1		T152	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T152	1		T153	1		T154	1
auto[TlIntgErrData]	partial	auto[0]	65	1			T50	9		T87	1		T88	3
auto[TlIntgErrData]	partial	auto[1]	58	1			T50	5		T87	3		T88	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T87	1		T152	2		T151	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T88	1		T104	1		T151	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T50	4		T87	1		T104	4
auto[TlIntgErrBoth]	partial	auto[1]	69	1			T50	1		T87	4		T88	1
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T105	1		T151	2		T155	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T87	2		T104	1		T156	1