Unified Coverage Report :: Module :: prim_generic_ram_1r1w

Module : prim_generic_ram_1r1w

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1r1w

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1r1w

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	652366655	3491567	0	0
gen_wmask[1].MaskCheckPortA_A	652366655	3491567	0	0
gen_wmask[2].MaskCheckPortA_A	652366655	3491567	0	0
gen_wmask[3].MaskCheckPortA_A	652366655	3491567	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652366655	3491567	0	0
T2	7304	142	0	0
T3	958096	832	0	0
T4	21793	204	0	0
T5	27625	224	0	0
T6	5157	0	0	0
T7	464949	3092	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	496184	7122	0	0
T12	270363	7590	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652366655	3491567	0	0
T2	7304	142	0	0
T3	958096	832	0	0
T4	21793	204	0	0
T5	27625	224	0	0
T6	5157	0	0	0
T7	464949	3092	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	496184	7122	0	0
T12	270363	7590	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652366655	3491567	0	0
T2	7304	142	0	0
T3	958096	832	0	0
T4	21793	204	0	0
T5	27625	224	0	0
T6	5157	0	0	0
T7	464949	3092	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	496184	7122	0	0
T12	270363	7590	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	652366655	3491567	0	0
T2	7304	142	0	0
T3	958096	832	0	0
T4	21793	204	0	0
T5	27625	224	0	0
T6	5157	0	0	0
T7	464949	3092	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	496184	7122	0	0
T12	270363	7590	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			==> MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T2,T3,T4

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	491149234	2147405	0	0
gen_wmask[1].MaskCheckPortA_A	491149234	2147405	0	0
gen_wmask[2].MaskCheckPortA_A	491149234	2147405	0	0
gen_wmask[3].MaskCheckPortA_A	491149234	2147405	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2147405	0	0
T2	4608	28	0	0
T3	852048	832	0	0
T4	19252	20	0	0
T5	18945	108	0	0
T6	5157	0	0	0
T7	387849	734	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6656	0	0
T12	0	6656	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2147405	0	0
T2	4608	28	0	0
T3	852048	832	0	0
T4	19252	20	0	0
T5	18945	108	0	0
T6	5157	0	0	0
T7	387849	734	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6656	0	0
T12	0	6656	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2147405	0	0
T2	4608	28	0	0
T3	852048	832	0	0
T4	19252	20	0	0
T5	18945	108	0	0
T6	5157	0	0	0
T7	387849	734	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6656	0	0
T12	0	6656	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2147405	0	0
T2	4608	28	0	0
T3	852048	832	0	0
T4	19252	20	0	0
T5	18945	108	0	0
T6	5157	0	0	0
T7	387849	734	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6656	0	0
T12	0	6656	0	0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		11	11	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	66	4	4	100.00
ALWAYS	77	2	2	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
45	1	1
54	4	4
66	1	1
67	1	1
68	1	1
69	1	1
			MISSING_ELSE
			MISSING_ELSE
77	1	1
78	1	1
			MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	66	2	2	100.00
IF	77	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv' or '../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	66	if (a_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T2,T3,T4

	LineNo.	Expression
-1-:	77	if (b_req_i)

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_wmask[0].MaskCheckPortA_A	161217421	1344162	0	0
gen_wmask[1].MaskCheckPortA_A	161217421	1344162	0	0
gen_wmask[2].MaskCheckPortA_A	161217421	1344162	0	0
gen_wmask[3].MaskCheckPortA_A	161217421	1344162	0	0

gen_wmask[0].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	1344162	0	0
T2	2696	114	0	0
T3	106048	0	0	0
T4	2541	184	0	0
T5	8680	116	0	0
T7	77100	2358	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

gen_wmask[1].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	1344162	0	0
T2	2696	114	0	0
T3	106048	0	0	0
T4	2541	184	0	0
T5	8680	116	0	0
T7	77100	2358	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

gen_wmask[2].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	1344162	0	0
T2	2696	114	0	0
T3	106048	0	0	0
T4	2541	184	0	0
T5	8680	116	0	0
T7	77100	2358	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0

gen_wmask[3].MaskCheckPortA_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	1344162	0	0
T2	2696	114	0	0
T3	106048	0	0	0
T4	2541	184	0	0
T5	8680	116	0	0
T7	77100	2358	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	0	264	0	0
T15	0	16889	0	0
T16	0	19865	0	0
T17	0	15591	0	0