Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	493555029	2959235	0	0
DepthKnown_A	493555029	493421096	0	0
RvalidKnown_A	493555029	493421096	0	0
WreadyKnown_A	493555029	493421096	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	2959235	0	0
T3	852048	832	0	0
T4	19252	0	0	0
T5	18945	0	0	0
T6	5157	0	0	0
T7	387849	0	0	0
T8	15785	832	0	0
T9	184322	2495	0	0
T10	9171	1663	0	0
T11	224332	9168	0	0
T12	601515	9980	0	0
T13	0	9149	0	0
T14	0	1663	0	0
T15	0	18317	0	0
T16	0	17484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	493555029	3212391	0	0
DepthKnown_A	493555029	493421096	0	0
RvalidKnown_A	493555029	493421096	0	0
WreadyKnown_A	493555029	493421096	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	3212391	0	0
T3	852048	832	0	0
T4	19252	0	0	0
T5	18945	0	0	0
T6	5157	0	0	0
T7	387849	0	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	21377	0	0
T12	601515	6656	0	0
T13	0	6656	0	0
T14	0	832	0	0
T15	0	22936	0	0
T16	0	19454	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	493555029	200579	0	0
DepthKnown_A	493555029	493421096	0	0
RvalidKnown_A	493555029	493421096	0	0
WreadyKnown_A	493555029	493421096	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	200579	0	0
T2	4608	29	0	0
T3	852048	0	0	0
T4	19252	46	0	0
T5	18945	30	0	0
T6	5157	0	0	0
T7	387849	608	0	0
T8	15785	0	0	0
T9	184322	0	0	0
T10	9171	0	0	0
T11	224332	110	0	0
T12	0	160	0	0
T13	0	64	0	0
T15	0	2012	0	0
T16	0	3208	0	0
T17	0	2047	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	493555029	469575	0	0
DepthKnown_A	493555029	493421096	0	0
RvalidKnown_A	493555029	493421096	0	0
WreadyKnown_A	493555029	493421096	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	469575	0	0
T2	4608	86	0	0
T3	852048	0	0	0
T4	19252	46	0	0
T5	18945	30	0	0
T6	5157	0	0	0
T7	387849	608	0	0
T8	15785	0	0	0
T9	184322	0	0	0
T10	9171	0	0	0
T11	224332	485	0	0
T12	0	160	0	0
T13	0	64	0	0
T15	0	8941	0	0
T16	0	10196	0	0
T17	0	9182	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	493555029	6560393	0	0
DepthKnown_A	493555029	493421096	0	0
RvalidKnown_A	493555029	493421096	0	0
WreadyKnown_A	493555029	493421096	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	6560393	0	0
T1	989	27	0	0
T2	4608	225	0	0
T3	852048	58	0	0
T4	19252	1757	0	0
T5	18945	481	0	0
T6	5157	126	0	0
T7	387849	7090	0	0
T8	15785	550	0	0
T9	184322	462	0	0
T10	9171	339	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	493555029	13597449	0	0
DepthKnown_A	493555029	493421096	0	0
RvalidKnown_A	493555029	493421096	0	0
WreadyKnown_A	493555029	493421096	0	0
gen_passthru_fifo.paramCheckPass	1130	1130	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	13597449	0	0
T1	989	27	0	0
T2	4608	1007	0	0
T3	852048	58	0	0
T4	19252	1757	0	0
T5	18945	476	0	0
T6	5157	597	0	0
T7	387849	7029	0	0
T8	15785	550	0	0
T9	184322	461	0	0
T10	9171	930	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	493555029	493421096	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1130	1130	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0