Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Unreachable
1	1	Covered	T11,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	813584076	650845956	0	0
CheckNGreaterZero_A	2865	2865	0	0
GntImpliesReady_A	813584076	3897855	0	0
GntImpliesValid_A	813584076	3897855	0	0
GrantKnown_A	813584076	650845956	0	0
IdxKnown_A	813584076	650845956	0	0
IndexIsCorrect_A	813584076	3897855	0	0
LockArbDecision_A	813584076	0	0	0
NoReadyValidNoGrant_A	813584076	0	0	0
ReadyAndValidImplyGrant_A	813584076	3897855	0	0
ReqAndReadyImplyGrant_A	813584076	3897855	0	0
ReqImpliesValid_A	813584076	3897855	0	0
ReqStaysHighUntilGranted0_M	813584076	0	0	0
RoundRobin_A	813584076	2	0	955
ValidKnown_A	813584076	650845956	0	0
gen_data_port_assertion.DataFlow_A	813584076	3897855	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	650845956	0	0
T1	989	935	0	0
T2	7304	7209	0	0
T3	1064144	957799	0	0
T4	24334	21524	0	0
T5	36305	27527	0	0
T6	5157	4912	0	0
T7	542049	460873	0	0
T8	49133	32381	0	0
T9	295996	239255	0	0
T10	43587	26279	0	0
T11	543704	270505	0	0
T12	540726	267642	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	1112321	0	0
T16	0	1208045	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2865	2865	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	650845956	0	0
T1	989	935	0	0
T2	7304	7209	0	0
T3	1064144	957799	0	0
T4	24334	21524	0	0
T5	36305	27527	0	0
T6	5157	4912	0	0
T7	542049	460873	0	0
T8	49133	32381	0	0
T9	295996	239255	0	0
T10	43587	26279	0	0
T11	543704	270505	0	0
T12	540726	267642	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	1112321	0	0
T16	0	1208045	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	650845956	0	0
T1	989	935	0	0
T2	7304	7209	0	0
T3	1064144	957799	0	0
T4	24334	21524	0	0
T5	36305	27527	0	0
T6	5157	4912	0	0
T7	542049	460873	0	0
T8	49133	32381	0	0
T9	295996	239255	0	0
T10	43587	26279	0	0
T11	543704	270505	0	0
T12	540726	267642	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	1112321	0	0
T16	0	1208045	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	2	0	955
T16	655083	1	0	1
T17	762920	0	0	1
T32	22753	0	0	1
T33	192728	0	0	1
T37	134117	0	0	1
T41	7864	0	0	1
T42	21048	0	0	1
T43	0	1	0	0
T44	1191	0	0	1
T45	93078	0	0	1
T46	9802	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	650845956	0	0
T1	989	935	0	0
T2	7304	7209	0	0
T3	1064144	957799	0	0
T4	24334	21524	0	0
T5	36305	27527	0	0
T6	5157	4912	0	0
T7	542049	460873	0	0
T8	49133	32381	0	0
T9	295996	239255	0	0
T10	43587	26279	0	0
T11	543704	270505	0	0
T12	540726	267642	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	1112321	0	0
T16	0	1208045	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	813584076	3897855	0	0
T2	7304	201	0	0
T3	958096	832	0	0
T4	21793	272	0	0
T5	27625	368	0	0
T6	5157	0	0	0
T7	464949	4505	0	0
T8	32459	832	0	0
T9	240159	1664	0	0
T10	26379	832	0	0
T11	768036	7254	0	0
T12	540726	7767	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	19111	0	0
T16	122599	24392	0	0
T17	225074	18591	0	0
T24	0	5739	0	0
T25	0	145	0	0
T31	0	4763	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T4,T5

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T5
1	0	Unreachable
1	1	Covered	T2,T4,T5

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T4,T5
0	0	1	Unreachable
0	0	0	Covered	T2,T4,T5

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	161217421	29276689	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	161217421	670839	0	0
GntImpliesValid_A	161217421	670839	0	0
GrantKnown_A	161217421	29276689	0	0
IdxKnown_A	161217421	29276689	0	0
IndexIsCorrect_A	161217421	670839	0	0
LockArbDecision_A	161217421	0	0	0
NoReadyValidNoGrant_A	161217421	0	0	0
ReadyAndValidImplyGrant_A	161217421	670839	0	0
ReqAndReadyImplyGrant_A	161217421	670839	0	0
ReqImpliesValid_A	161217421	670839	0	0
ReqStaysHighUntilGranted0_M	161217421	0	0	0
RoundRobin_A	161217421	0	0	0
ValidKnown_A	161217421	29276689	0	0
gen_data_port_assertion.DataFlow_A	161217421	670839	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	29276689	0	0
T2	2696	2696	0	0
T3	106048	0	0	0
T4	2541	2368	0	0
T5	8680	8680	0	0
T7	77100	73088	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	3	0	0
T15	0	192947	0	0
T16	0	333048	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	29276689	0	0
T2	2696	2696	0	0
T3	106048	0	0	0
T4	2541	2368	0	0
T5	8680	8680	0	0
T7	77100	73088	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	3	0	0
T15	0	192947	0	0
T16	0	333048	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	29276689	0	0
T2	2696	2696	0	0
T3	106048	0	0	0
T4	2541	2368	0	0
T5	8680	8680	0	0
T7	77100	73088	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	3	0	0
T15	0	192947	0	0
T16	0	333048	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	29276689	0	0
T2	2696	2696	0	0
T3	106048	0	0	0
T4	2541	2368	0	0
T5	8680	8680	0	0
T7	77100	73088	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	3	0	0
T15	0	192947	0	0
T16	0	333048	0	0
T17	0	873952	0	0
T23	0	59760	0	0
T24	0	105976	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	670839	0	0
T2	2696	144	0	0
T3	106048	0	0	0
T4	2541	206	0	0
T5	8680	230	0	0
T7	77100	3163	0	0
T8	16674	0	0	0
T9	55837	0	0	0
T10	17208	0	0	0
T11	271852	0	0	0
T12	270363	0	0	0
T15	0	6721	0	0
T16	0	13217	0	0
T17	0	8820	0	0
T24	0	5097	0	0
T25	0	145	0	0
T31	0	3517	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T12,T13

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Unreachable
1	1	Covered	T11,T12,T13

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T11,T12,T13
0	0	1	Unreachable
0	0	0	Covered	T3,T8,T9

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	161217421	130508809	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	161217421	892729	0	0
GntImpliesValid_A	161217421	892729	0	0
GrantKnown_A	161217421	130508809	0	0
IdxKnown_A	161217421	130508809	0	0
IndexIsCorrect_A	161217421	892729	0	0
LockArbDecision_A	161217421	0	0	0
NoReadyValidNoGrant_A	161217421	0	0	0
ReadyAndValidImplyGrant_A	161217421	892729	0	0
ReqAndReadyImplyGrant_A	161217421	892729	0	0
ReqImpliesValid_A	161217421	892729	0	0
ReqStaysHighUntilGranted0_M	161217421	0	0	0
RoundRobin_A	161217421	0	0	0
ValidKnown_A	161217421	130508809	0	0
gen_data_port_assertion.DataFlow_A	161217421	892729	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	130508809	0	0
T3	106048	105844	0	0
T4	2541	0	0	0
T5	8680	0	0	0
T7	77100	0	0	0
T8	16674	16674	0	0
T9	55837	55012	0	0
T10	17208	17208	0	0
T11	271852	270505	0	0
T12	270363	267639	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	919374	0	0
T16	0	874997	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	130508809	0	0
T3	106048	105844	0	0
T4	2541	0	0	0
T5	8680	0	0	0
T7	77100	0	0	0
T8	16674	16674	0	0
T9	55837	55012	0	0
T10	17208	17208	0	0
T11	271852	270505	0	0
T12	270363	267639	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	919374	0	0
T16	0	874997	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	130508809	0	0
T3	106048	105844	0	0
T4	2541	0	0	0
T5	8680	0	0	0
T7	77100	0	0	0
T8	16674	16674	0	0
T9	55837	55012	0	0
T10	17208	17208	0	0
T11	271852	270505	0	0
T12	270363	267639	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	919374	0	0
T16	0	874997	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	130508809	0	0
T3	106048	105844	0	0
T4	2541	0	0	0
T5	8680	0	0	0
T7	77100	0	0	0
T8	16674	16674	0	0
T9	55837	55012	0	0
T10	17208	17208	0	0
T11	271852	270505	0	0
T12	270363	267639	0	0
T13	498976	497415	0	0
T14	0	13744	0	0
T15	0	919374	0	0
T16	0	874997	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	161217421	892729	0	0
T11	271852	466	0	0
T12	270363	934	0	0
T13	498976	264	0	0
T14	13744	0	0	0
T15	112199	12390	0	0
T16	122599	11175	0	0
T17	225074	9771	0	0
T24	0	642	0	0
T31	0	1246	0	0
T32	15327	0	0	0
T33	63007	0	0	0
T34	0	7947	0	0
T38	0	9458	0	0
T41	5088	0	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T5

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T5
1	0	Covered	T2,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T2,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	491149234	491060458	0	0
CheckNGreaterZero_A	955	955	0	0
GntImpliesReady_A	491149234	2334287	0	0
GntImpliesValid_A	491149234	2334287	0	0
GrantKnown_A	491149234	491060458	0	0
IdxKnown_A	491149234	491060458	0	0
IndexIsCorrect_A	491149234	2334287	0	0
LockArbDecision_A	491149234	0	0	0
NoReadyValidNoGrant_A	491149234	0	0	0
ReadyAndValidImplyGrant_A	491149234	2334287	0	0
ReqAndReadyImplyGrant_A	491149234	2334287	0	0
ReqImpliesValid_A	491149234	2334287	0	0
ReqStaysHighUntilGranted0_M	491149234	0	0	0
RoundRobin_A	491149234	2	0	955
ValidKnown_A	491149234	491060458	0	0
gen_data_port_assertion.DataFlow_A	491149234	2334287	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	491060458	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	491060458	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	491060458	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2	0	955
T16	655083	1	0	1
T17	762920	0	0	1
T32	22753	0	0	1
T33	192728	0	0	1
T37	134117	0	0	1
T41	7864	0	0	1
T42	21048	0	0	1
T43	0	1	0	0
T44	1191	0	0	1
T45	93078	0	0	1
T46	9802	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	491060458	0	0
T1	989	935	0	0
T2	4608	4513	0	0
T3	852048	851955	0	0
T4	19252	19156	0	0
T5	18945	18847	0	0
T6	5157	4912	0	0
T7	387849	387785	0	0
T8	15785	15707	0	0
T9	184322	184243	0	0
T10	9171	9071	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491149234	2334287	0	0
T2	4608	57	0	0
T3	852048	832	0	0
T4	19252	66	0	0
T5	18945	138	0	0
T6	5157	0	0	0
T7	387849	1342	0	0
T8	15785	832	0	0
T9	184322	1664	0	0
T10	9171	832	0	0
T11	224332	6788	0	0
T12	0	6833	0	0