Unified Coverage Report :: Module

Module : spid_dpram

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	75.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spid_dpram	91.67	100.00	75.00			100.00

Module Instance : tb.dut.u_spid_dpram

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	75.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.52	95.20	84.31	97.00		90.62	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ram1r1w.u_spi2sys_mem	100.00	100.00				100.00	100.00
gen_ram1r1w.u_sys2spi_mem	100.00	100.00				100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : spid_dpram

	Line No.	Total	Covered	Percent
TOTAL		18	18	100.00
CONT_ASSIGN	64	1	1	100.00
CONT_ASSIGN	65	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	83	1	1	100.00
CONT_ASSIGN	84	1	1	100.00
CONT_ASSIGN	91	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
ALWAYS	103	7	7	100.00
ALWAYS	118	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
64	1	1
65	1	1
70	1	1
71	1	1
83	1	1
84	1	1
91	1	1
92	1	1
103	1	1
105	1	1
106	1	1
108	1	1
110	1	1
111	1	1
113	1	1
			MISSING_ELSE
118	1	1
119	1	1
121	1	1

Cond Coverage for Module : spid_dpram

	Total	Covered	Percent
Conditions	16	12	75.00
Logical	16	12	75.00
Non-Logical	0	0
Event	0	0

 LINE       64
 EXPRESSION ((sys_addr_i < Sys2SpiEnd) & sys_req_i & sys_write_i)
             ------------1------------   ----2----   -----3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T4

 LINE       70
 EXPRESSION (spi_req_i & ((!spi_write_i)))
             ----1----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T3,T4

 LINE       83
 EXPRESSION (spi_req_i & spi_write_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       91
 EXPRESSION (sys_req_i & ((!sys_write_i)))
             ----1----   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T4,T5

 LINE       108
 EXPRESSION (spi2sys_wr_req && ((!initialized_words_q[7'(spi2sys_wr_addr)])))
             -------1------    ----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T4,T5
1	1	Covered	T2,T4,T5

Branch Coverage for Module : spid_dpram

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	108	2	2	100.00
IF	118	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv' or '../src/lowrisc_ip_spi_device_0.1/rtl/spid_dpram.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	108	if ((spi2sys_wr_req && (!initialized_words_q[7'(spi2sys_wr_addr)])))

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T5
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	118	if ((!rst_spi_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T3,T4