Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3888604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4402185

1

T1

1

T3

9674

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4589542	1			T1	1		T2	69		T3	17584
values[0x0]	1850187	1			T3	436		T5	21		T6	874
values[0x1]	1851060	1			T3	481		T4	1		T5	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2750636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5540153

1

T1

1

T2

17

T3

11398

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30174	1			T3	91		T6	26		T9	31
valid_sources[0x01]	33114	1			T3	66		T6	25		T9	28
valid_sources[0x02]	29762	1			T3	55		T6	22		T9	47
valid_sources[0x03]	28923	1			T3	70		T6	19		T9	7
valid_sources[0x04]	32696	1			T2	1		T3	75		T6	36
valid_sources[0x05]	29395	1			T3	68		T6	35		T9	20
valid_sources[0x06]	31064	1			T3	69		T6	11		T9	40
valid_sources[0x07]	29533	1			T3	78		T6	31		T9	56
valid_sources[0x08]	30462	1			T3	83		T6	28		T9	32
valid_sources[0x09]	31343	1			T3	60		T6	4		T9	91
valid_sources[0x0a]	37657	1			T2	1		T3	62		T6	25
valid_sources[0x0b]	30360	1			T3	72		T6	18		T9	13
valid_sources[0x0c]	30403	1			T3	73		T6	20		T8	1
valid_sources[0x0d]	30399	1			T3	72		T6	13		T9	10
valid_sources[0x0e]	29727	1			T3	79		T6	19		T9	32
valid_sources[0x0f]	33008	1			T2	1		T3	74		T6	29
valid_sources[0x10]	31845	1			T3	78		T6	8		T9	12
valid_sources[0x11]	37804	1			T3	73		T6	57		T9	30
valid_sources[0x12]	35855	1			T3	79		T6	9		T9	62
valid_sources[0x13]	29945	1			T2	2		T3	71		T6	12
valid_sources[0x14]	30865	1			T2	2		T3	71		T6	13
valid_sources[0x15]	31469	1			T3	68		T6	18		T9	10
valid_sources[0x16]	30065	1			T2	3		T3	58		T6	17
valid_sources[0x17]	30506	1			T3	70		T6	20		T9	16
valid_sources[0x18]	32111	1			T3	78		T6	17		T9	61
valid_sources[0x19]	29046	1			T3	89		T6	18		T9	22
valid_sources[0x1a]	37608	1			T3	70		T6	24		T9	14
valid_sources[0x1b]	31951	1			T3	65		T6	17		T9	16
valid_sources[0x1c]	30063	1			T3	52		T6	17		T15	2
valid_sources[0x1d]	32073	1			T3	66		T6	23		T9	14
valid_sources[0x1e]	30908	1			T2	1		T3	84		T6	11
valid_sources[0x1f]	30102	1			T3	79		T6	18		T9	14
valid_sources[0x20]	30325	1			T3	73		T6	29		T9	33
valid_sources[0x21]	37162	1			T3	79		T6	28		T9	11
valid_sources[0x22]	30024	1			T3	66		T6	9		T9	79
valid_sources[0x23]	31389	1			T3	64		T6	18		T9	42
valid_sources[0x24]	31353	1			T2	1		T3	76		T6	15
valid_sources[0x25]	30459	1			T3	68		T6	35		T9	29
valid_sources[0x26]	30780	1			T3	67		T6	9		T9	32
valid_sources[0x27]	35606	1			T2	1		T3	86		T6	12
valid_sources[0x28]	32497	1			T3	79		T6	24		T9	20
valid_sources[0x29]	32624	1			T2	1		T3	70		T6	15
valid_sources[0x2a]	31249	1			T3	65		T6	16		T9	7
valid_sources[0x2b]	31214	1			T3	78		T6	24		T13	3
valid_sources[0x2c]	30656	1			T3	68		T6	22		T9	27
valid_sources[0x2d]	30666	1			T3	73		T4	1		T6	14
valid_sources[0x2e]	29702	1			T2	1		T3	74		T6	9
valid_sources[0x2f]	30750	1			T3	76		T6	36		T9	15
valid_sources[0x30]	34159	1			T3	65		T6	25		T9	68
valid_sources[0x31]	32005	1			T3	64		T6	8		T9	47
valid_sources[0x32]	29325	1			T2	1		T3	73		T6	22
valid_sources[0x33]	31872	1			T3	86		T6	31		T9	11
valid_sources[0x34]	31593	1			T2	1		T3	90		T6	17
valid_sources[0x35]	30484	1			T3	85		T6	12		T9	11
valid_sources[0x36]	31438	1			T3	79		T6	24		T9	54
valid_sources[0x37]	32614	1			T2	2		T3	93		T6	17
valid_sources[0x38]	30719	1			T3	72		T6	25		T9	6
valid_sources[0x39]	33388	1			T2	2		T3	67		T6	36
valid_sources[0x3a]	30145	1			T3	72		T6	21		T9	25
valid_sources[0x3b]	32383	1			T3	73		T6	14		T9	20
valid_sources[0x3c]	29262	1			T2	1		T3	63		T6	28
valid_sources[0x3d]	45176	1			T3	88		T6	12		T9	42
valid_sources[0x3e]	31454	1			T3	63		T6	7		T9	49
valid_sources[0x3f]	29924	1			T3	68		T6	11		T9	17
valid_sources[0x40]	31557	1			T3	59		T6	14		T9	45
valid_sources[0x41]	35324	1			T3	66		T6	19		T9	11
valid_sources[0x42]	32329	1			T3	60		T6	11		T9	24
valid_sources[0x43]	32795	1			T3	71		T6	12		T9	8
valid_sources[0x44]	31204	1			T3	73		T6	17		T9	10
valid_sources[0x45]	29702	1			T3	69		T6	30		T9	36
valid_sources[0x46]	32641	1			T3	66		T6	24		T9	35
valid_sources[0x47]	32491	1			T3	68		T6	20		T9	47
valid_sources[0x48]	29350	1			T3	62		T6	14		T9	27
valid_sources[0x49]	29895	1			T3	66		T6	22		T9	20
valid_sources[0x4a]	37864	1			T1	1		T2	1		T3	67
valid_sources[0x4b]	40187	1			T2	1		T3	80		T6	22
valid_sources[0x4c]	34151	1			T3	63		T6	38		T9	53
valid_sources[0x4d]	32041	1			T3	65		T6	29		T9	20
valid_sources[0x4e]	32476	1			T3	67		T6	10		T9	56
valid_sources[0x4f]	32749	1			T3	74		T6	42		T9	5
valid_sources[0x50]	34222	1			T3	63		T6	11		T9	18
valid_sources[0x51]	33185	1			T3	66		T6	14		T9	23
valid_sources[0x52]	31511	1			T3	85		T6	25		T9	49
valid_sources[0x53]	33747	1			T3	77		T6	13		T9	14
valid_sources[0x54]	35493	1			T3	52		T6	13		T9	34
valid_sources[0x55]	30783	1			T3	64		T6	16		T9	29
valid_sources[0x56]	29523	1			T3	65		T6	13		T9	16
valid_sources[0x57]	29576	1			T3	89		T6	16		T9	24
valid_sources[0x58]	34901	1			T3	65		T6	11		T9	15
valid_sources[0x59]	30635	1			T3	60		T6	7		T9	31
valid_sources[0x5a]	35208	1			T3	70		T6	10		T9	34
valid_sources[0x5b]	30526	1			T3	71		T6	27		T7	150
valid_sources[0x5c]	32437	1			T3	75		T6	34		T9	22
valid_sources[0x5d]	30068	1			T3	77		T6	21		T9	18
valid_sources[0x5e]	29868	1			T3	72		T6	17		T9	30
valid_sources[0x5f]	30696	1			T3	89		T6	23		T9	46
valid_sources[0x60]	38457	1			T3	82		T6	22		T9	11
valid_sources[0x61]	71197	1			T3	66		T6	14		T9	2
valid_sources[0x62]	29293	1			T3	61		T6	28		T9	1
valid_sources[0x63]	30383	1			T3	64		T6	26		T9	12
valid_sources[0x64]	31275	1			T3	72		T6	16		T9	36
valid_sources[0x65]	31393	1			T3	57		T6	20		T9	5
valid_sources[0x66]	29720	1			T3	67		T6	32		T9	5
valid_sources[0x67]	33437	1			T3	91		T6	23		T9	25
valid_sources[0x68]	29728	1			T3	88		T6	19		T9	31
valid_sources[0x69]	33350	1			T3	67		T6	38		T9	60
valid_sources[0x6a]	32640	1			T3	80		T6	9		T9	44
valid_sources[0x6b]	29806	1			T3	72		T6	13		T9	6
valid_sources[0x6c]	31757	1			T3	76		T6	18		T9	59
valid_sources[0x6d]	33231	1			T3	73		T6	46		T9	17
valid_sources[0x6e]	32116	1			T2	1		T3	74		T6	16
valid_sources[0x6f]	32182	1			T3	76		T6	9		T9	16
valid_sources[0x70]	30146	1			T3	61		T6	24		T9	26
valid_sources[0x71]	30891	1			T3	64		T6	9		T9	19
valid_sources[0x72]	30550	1			T3	53		T6	28		T9	34
valid_sources[0x73]	32748	1			T2	1		T3	75		T6	16
valid_sources[0x74]	30269	1			T3	80		T6	23		T9	4
valid_sources[0x75]	30486	1			T3	62		T6	10		T9	41
valid_sources[0x76]	30788	1			T3	73		T6	23		T9	10
valid_sources[0x77]	30535	1			T3	85		T6	27		T9	27
valid_sources[0x78]	30759	1			T3	71		T6	26		T9	19
valid_sources[0x79]	30248	1			T3	82		T6	24		T9	15
valid_sources[0x7a]	34526	1			T3	83		T6	17		T9	4
valid_sources[0x7b]	31836	1			T2	1		T3	77		T6	32
valid_sources[0x7c]	30406	1			T3	96		T6	11		T9	20
valid_sources[0x7d]	31642	1			T3	67		T6	23		T9	3
valid_sources[0x7e]	35272	1			T3	72		T6	8		T9	15
valid_sources[0x7f]	32516	1			T3	74		T6	18		T8	1
valid_sources[0x80]	38559	1			T2	1		T3	62		T6	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1063386

1

T1

1

T3

8764

T4

1

values[0x0]

all_enables

biggest_size

1681934

1

T3

436

T5

16

T6

684

values[0x1]

all_enables

biggest_size

1656865

1

T3

474

T5

18

T6

654