Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3912024

1

T2

69

T3

8827

T4

1

full_word

4403597

1

T1

1

T3

9674

T4

1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8315241	1			T1	1		T2	69		T3	18501
auto[TlIntgErrCmd]	122	1			T106	2		T127	1		T129	2
auto[TlIntgErrData]	142	1			T106	4		T127	7		T129	1
auto[TlIntgErrBoth]	116	1			T106	4		T127	2		T129	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4594672

1

T1

1

T2

69

T3

17584

auto[1]

3720949

1

T3

917

T4

1

T5

43

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3530724	1			T2	69		T3	8820		T6	2725
auto[TlIntgErrNone]	partial	auto[1]	380956	1			T3	7		T4	1		T5	9
auto[TlIntgErrNone]	full_word	auto[0]	1063759	1			T1	1		T3	8764		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3339802	1			T3	910		T5	34		T6	1338
auto[TlIntgErrCmd]	partial	auto[0]	50	1			T106	1		T129	1		T145	3
auto[TlIntgErrCmd]	partial	auto[1]	65	1			T106	1		T127	1		T129	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T221	1		T142	1		T222	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T223	1		T224	1		T225	1
auto[TlIntgErrData]	partial	auto[0]	68	1			T106	1		T127	2		T145	9
auto[TlIntgErrData]	partial	auto[1]	60	1			T106	3		T127	3		T129	1
auto[TlIntgErrData]	full_word	auto[0]	8	1			T127	1		T217	1		T221	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T127	1		T226	1		T224	2
auto[TlIntgErrBoth]	partial	auto[0]	53	1			T106	2		T127	2		T129	4
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T106	2		T129	2		T145	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T226	1		T227	1		T225	1
auto[TlIntgErrBoth]	full_word	auto[1]	9	1			T129	1		T227	1		T218	1