Line Coverage for Module :
spi_s2p
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 20 | 20 | 100.00 |
| ALWAYS | 43 | 4 | 4 | 100.00 |
| ALWAYS | 63 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 71 | 1 | 1 | 100.00 |
| ALWAYS | 75 | 8 | 8 | 100.00 |
| ALWAYS | 91 | 4 | 4 | 100.00 |
42 always_comb begin
43 1/1 unique case (io_mode_i)
Tests: T1 T2 T3
44 SingleIO: begin
45 1/1 data_d = (order_i) ? {s_i[0], data_q[7:1]} : {data_q[6:0], s_i[0]};
Tests: T1 T2 T3
46 end
47
48 DualIO: begin
49 1/1 data_d = (order_i) ? {s_i[1:0], data_q[7:2]} : {data_q[5:0], s_i[1:0]};
Tests: T1 T2 T3
50 end
51
52 QuadIO: begin
53 1/1 data_d = (order_i) ? {s_i[3:0], data_q[7:4]} : {data_q[3:0], s_i[3:0]};
Tests: T1 T2 T3
54 end
55
56 default: begin
57 data_d = data_q;
58 end
59 endcase
60 end
61
62 always_ff @(posedge clk_i or negedge rst_ni) begin
63 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
64 1/1 data_q <= '0;
Tests: T1 T2 T3
65 end else begin
66 1/1 data_q <= data_d;
Tests: T3 T13 T15
67 end
68 end
69
70 // send un-latched data
71 1/1 assign data_o = data_d;
Tests: T1 T2 T3
72
73 // Bitcount in a byte
74 always_ff @(posedge clk_i or negedge rst_ni) begin
75 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
76 1/1 cnt <= count_t'(Bits-1);
Tests: T1 T2 T3
77 1/1 end else if (cnt == '0) begin
Tests: T3 T13 T15
78 1/1 cnt <= count_t'(Bits-1);
Tests: T3 T13 T15
79 end else begin
80 1/1 unique case (io_mode_i)
Tests: T3 T13 T15
81 1/1 SingleIO: cnt <= cnt - count_t'('h1);
Tests: T3 T13 T15
82 1/1 DualIO: cnt <= cnt - count_t'('h2);
Tests: T3 T23 T40
83 1/1 QuadIO: cnt <= cnt - count_t'('h4);
Tests: T3 T16 T18
84 default: cnt <= cnt;
85 endcase
86 end
87 end
88
89 // data valid
90 always_comb begin
91 1/1 unique case (io_mode_i)
Tests: T1 T2 T3
92 1/1 SingleIO: data_valid_o = (cnt == 'h0);
Tests: T1 T2 T3
93 1/1 DualIO: data_valid_o = (cnt == 'h1);
Tests: T1 T2 T3
94 1/1 QuadIO: data_valid_o = (cnt == 'h3);
Tests: T1 T2 T3
95 default: data_valid_o = 1'b 0;
Cond Coverage for Module :
spi_s2p
| Total | Covered | Percent |
|---|
| Conditions | 14 | 11 | 78.57 |
| Logical | 14 | 11 | 78.57 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 45
EXPRESSION (order_i ? ({s_i[0], data_q[7:1]}) : ({data_q[6:0], s_i[0]}))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 49
EXPRESSION (order_i ? ({s_i[1:0], data_q[7:2]}) : ({data_q[5:0], s_i[1:0]}))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 53
EXPRESSION (order_i ? ({s_i[3:0], data_q[7:4]}) : ({data_q[3:0], s_i[3:0]}))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 77
EXPRESSION (cnt == '0)
-----1-----
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T13,T15 |
| 1 | Covered | T3,T13,T15 |
LINE 92
EXPRESSION (cnt == 3'b0)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T13,T15 |
LINE 93
EXPRESSION (cnt == 3'b1)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T3,T23,T50 |
LINE 94
EXPRESSION (cnt == 3'h3)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T16,T23,T40 |
Branch Coverage for Module :
spi_s2p
| Line No. | Total | Covered | Percent |
| Branches |
|
19 |
15 |
78.95 |
| CASE |
43 |
7 |
4 |
57.14 |
| IF |
63 |
2 |
2 |
100.00 |
| IF |
75 |
6 |
5 |
83.33 |
| CASE |
91 |
4 |
4 |
100.00 |
43 unique case (io_mode_i)
-1-
44 SingleIO: begin
45 data_d = (order_i) ? {s_i[0], data_q[7:1]} : {data_q[6:0], s_i[0]};
-2-
==>
==>
46 end
47
48 DualIO: begin
49 data_d = (order_i) ? {s_i[1:0], data_q[7:2]} : {data_q[5:0], s_i[1:0]};
-3-
==>
==>
50 end
51
52 QuadIO: begin
53 data_d = (order_i) ? {s_i[3:0], data_q[7:4]} : {data_q[3:0], s_i[3:0]};
-4-
==>
==>
54 end
55
56 default: begin
57 data_d = data_q;
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| SingleIO |
1 |
- |
- |
Not Covered |
|
| SingleIO |
0 |
- |
- |
Covered |
T1,T2,T3 |
| DualIO |
- |
1 |
- |
Not Covered |
|
| DualIO |
- |
0 |
- |
Covered |
T1,T2,T3 |
| QuadIO |
- |
- |
1 |
Not Covered |
|
| QuadIO |
- |
- |
0 |
Covered |
T1,T2,T3 |
| default |
- |
- |
- |
Covered |
T1,T2,T3 |
63 if (!rst_ni) begin
-1-
64 data_q <= '0;
==>
65 end else begin
66 data_q <= data_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T3,T13,T15 |
75 if (!rst_ni) begin
-1-
76 cnt <= count_t'(Bits-1);
==>
77 end else if (cnt == '0) begin
-2-
78 cnt <= count_t'(Bits-1);
==>
79 end else begin
80 unique case (io_mode_i)
-3-
81 SingleIO: cnt <= cnt - count_t'('h1);
==>
82 DualIO: cnt <= cnt - count_t'('h2);
==>
83 QuadIO: cnt <= cnt - count_t'('h4);
==>
84 default: cnt <= cnt;
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T3,T13,T15 |
| 0 |
0 |
SingleIO |
Covered |
T3,T13,T15 |
| 0 |
0 |
DualIO |
Covered |
T3,T23,T40 |
| 0 |
0 |
QuadIO |
Covered |
T3,T16,T18 |
| 0 |
0 |
default |
Not Covered |
|
91 unique case (io_mode_i)
-1-
92 SingleIO: data_valid_o = (cnt == 'h0);
==>
93 DualIO: data_valid_o = (cnt == 'h1);
==>
94 QuadIO: data_valid_o = (cnt == 'h3);
==>
95 default: data_valid_o = 1'b 0;
==>
Branches:
| -1- | Status | Tests |
| SingleIO |
Covered |
T1,T2,T3 |
| DualIO |
Covered |
T1,T2,T3 |
| QuadIO |
Covered |
T1,T2,T3 |
| default |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
spi_s2p
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
|
IoModeDefault_A |
150126960 |
21469 |
0 |
0 |
IoModeDefault_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
150126960 |
21469 |
0 |
0 |
| T3 |
57491 |
3 |
0 |
0 |
| T5 |
1008 |
0 |
0 |
0 |
| T6 |
59612 |
0 |
0 |
0 |
| T7 |
22059 |
0 |
0 |
0 |
| T9 |
91883 |
0 |
0 |
0 |
| T13 |
4208 |
1 |
0 |
0 |
| T14 |
864 |
0 |
0 |
0 |
| T15 |
13132 |
2 |
0 |
0 |
| T16 |
20820 |
1 |
0 |
0 |
| T17 |
4176 |
1 |
0 |
0 |
| T18 |
0 |
2 |
0 |
0 |
| T19 |
0 |
2 |
0 |
0 |
| T20 |
0 |
3 |
0 |
0 |
| T22 |
0 |
2 |
0 |
0 |
| T23 |
0 |
6 |
0 |
0 |