Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490607002	2906659	0	0
DepthKnown_A	490607002	490477739	0	0
RvalidKnown_A	490607002	490477739	0	0
WreadyKnown_A	490607002	490477739	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	2906659	0	0
T3	463556	1663	0	0
T4	999	0	0	0
T5	3420	0	0	0
T6	239225	0	0	0
T7	30356	0	0	0
T8	1281	0	0	0
T9	273011	0	0	0
T10	917	0	0	0
T11	1162	0	0	0
T12	7532	0	0	0
T13	0	832	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	1670	0	0
T18	0	2876	0	0
T19	0	832	0	0
T20	0	1664	0	0
T22	0	1663	0	0
T23	0	7485	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490607002	3179448	0	0
DepthKnown_A	490607002	490477739	0	0
RvalidKnown_A	490607002	490477739	0	0
WreadyKnown_A	490607002	490477739	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	3179448	0	0
T3	463556	832	0	0
T4	999	0	0	0
T5	3420	0	0	0
T6	239225	0	0	0
T7	30356	0	0	0
T8	1281	0	0	0
T9	273011	0	0	0
T10	917	0	0	0
T11	1162	0	0	0
T12	7532	0	0	0
T13	0	2582	0	0
T15	0	832	0	0
T16	0	832	0	0
T17	0	839	0	0
T18	0	1856	0	0
T19	0	2641	0	0
T20	0	833	0	0
T22	0	832	0	0
T23	0	4992	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490607002	199371	0	0
DepthKnown_A	490607002	490477739	0	0
RvalidKnown_A	490607002	490477739	0	0
WreadyKnown_A	490607002	490477739	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	199371	0	0
T6	239225	366	0	0
T7	30356	0	0	0
T8	1281	0	0	0
T9	273011	635	0	0
T10	917	0	0	0
T11	1162	0	0	0
T12	7532	0	0	0
T13	10204	0	0	0
T14	4145	0	0	0
T23	0	129	0	0
T29	0	21	0	0
T38	652	0	0	0
T44	0	10	0	0
T45	0	38	0	0
T46	0	627	0	0
T47	0	728	0	0
T48	0	871	0	0
T49	0	128	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490607002	449251	0	0
DepthKnown_A	490607002	490477739	0	0
RvalidKnown_A	490607002	490477739	0	0
WreadyKnown_A	490607002	490477739	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	449251	0	0
T6	239225	1154	0	0
T7	30356	0	0	0
T8	1281	0	0	0
T9	273011	635	0	0
T10	917	0	0	0
T11	1162	0	0	0
T12	7532	0	0	0
T13	10204	0	0	0
T14	4145	0	0	0
T23	0	129	0	0
T29	0	105	0	0
T38	652	0	0	0
T44	0	52	0	0
T45	0	38	0	0
T46	0	627	0	0
T47	0	728	0	0
T48	0	871	0	0
T49	0	596	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490607002	6601535	0	0
DepthKnown_A	490607002	490477739	0	0
RvalidKnown_A	490607002	490477739	0	0
WreadyKnown_A	490607002	490477739	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	6601535	0	0
T1	1752	1	0	0
T2	1653	69	0	0
T3	463556	17669	0	0
T4	999	2	0	0
T5	3420	44	0	0
T6	239225	4694	0	0
T7	30356	150	0	0
T8	1281	3	0	0
T9	273011	6213	0	0
T10	917	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	490607002	14071220	0	0
DepthKnown_A	490607002	490477739	0	0
RvalidKnown_A	490607002	490477739	0	0
WreadyKnown_A	490607002	490477739	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	14071220	0	0
T1	1752	1	0	0
T2	1653	69	0	0
T3	463556	17669	0	0
T4	999	2	0	0
T5	3420	44	0	0
T6	239225	14328	0	0
T7	30356	388	0	0
T8	1281	19	0	0
T9	273011	6160	0	0
T10	917	15	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	490607002	490477739	0	0
T1	1752	1661	0	0
T2	1653	1564	0	0
T3	463556	463466	0	0
T4	999	939	0	0
T5	3420	3369	0	0
T6	239225	239167	0	0
T7	30356	30295	0	0
T8	1281	1215	0	0
T9	273011	272919	0	0
T10	917	832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0