Line Coverage for Module :
spid_readbuffer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 49 | 43 | 87.76 |
| ALWAYS | 105 | 6 | 4 | 66.67 |
| ALWAYS | 130 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 141 | 1 | 1 | 100.00 |
| ALWAYS | 147 | 6 | 5 | 83.33 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| ALWAYS | 163 | 8 | 7 | 87.50 |
| ALWAYS | 177 | 6 | 5 | 83.33 |
| ALWAYS | 196 | 5 | 5 | 100.00 |
| ALWAYS | 205 | 8 | 8 | 100.00 |
104 always_ff @(posedge sys_clk_i or negedge sys_rst_ni) begin
105 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
106 1/1 sys_clr_req <= 1'b0;
Tests: T1 T2 T3
107 1/1 end else if (sys_clr_i) begin
Tests: T1 T2 T3
108 0/1 ==> sys_clr_req <= 1'b1;
109 1/1 end else if (sys_clr_ack) begin
Tests: T1 T2 T3
110 0/1 ==> sys_clr_req <= 1'b0;
111 end
MISSING_ELSE
112 end
113
114 prim_sync_reqack u_sys2spi_clr (
115 .clk_src_i (sys_clk_i),
116 .rst_src_ni (sys_rst_ni),
117 .clk_dst_i (clk_i),
118 .rst_dst_ni (sys_rst_ni),
119
120 .req_chk_i (1'b1),
121
122 .src_req_i (sys_clr_req),
123 .src_ack_o (sys_clr_ack),
124 .dst_req_o (spi_clr),
125 .dst_ack_i (spi_clr)
126 );
127
128 // Flip event handling
129 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
130 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
131 1/1 next_buffer_addr <= (32-SramBufferAw)'(1); // pointing to next buffer
Tests: T1 T2 T3
132 1/1 end else if (spi_clr) begin
Tests: T3 T5 T6
133 0/1 ==> next_buffer_addr <= (32-SramBufferAw)'(1); // pointing to next buffer
134 1/1 end else if (active && flip) begin
Tests: T3 T5 T6
135 1/1 next_buffer_addr <= next_buffer_addr + 1'b 1;
Tests: T18 T40 T51
136 end
MISSING_ELSE
137 end
138
139 logic [31-SramBufferAw:0] current_buffer_idx;
140 1/1 assign current_buffer_idx = current_address_i[31:SramBufferAw];
Tests: T1 T2 T3
141 1/1 assign flip = current_buffer_idx == next_buffer_addr;
Tests: T1 T2 T3
142
143 // make flip event single cycle pulse signal
144 // It will be synchronized into the bus clock domain using prim_pulse_sync
145 logic flip_q;
146 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
147 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
148 1/1 flip_q <= 1'b 0;
Tests: T1 T2 T3
149 1/1 end else if (spi_clr) begin
Tests: T3 T5 T6
150 0/1 ==> flip_q <= 1'b 0;
151 1/1 end else if (active) begin
Tests: T3 T5 T6
152 1/1 flip_q <= flip;
Tests: T18 T40 T51
153 end
MISSING_ELSE
154 end
155
156 1/1 assign event_flip_o = active && flip && !flip_q;
Tests: T1 T2 T3
157
158 // Watermark event: Threshold should not be 0 to enable the event
159 1/1 assign watermark_cross = (current_address_i[SramBufferAw-1:0] >= threshold_i)
Tests: T1 T2 T3
160 && |threshold_i;
161
162 always_ff @(posedge clk_i or negedge sys_rst_ni) begin
163 1/1 if (!sys_rst_ni) begin
Tests: T1 T2 T3
164 1/1 watermark_crossed <= 1'b 0;
Tests: T1 T2 T3
165 1/1 end else if (spi_clr) begin
Tests: T3 T5 T6
166 0/1 ==> watermark_crossed <= 1'b 0;
167 1/1 end else if (active && watermark_cross) begin
Tests: T3 T5 T6
168 // When `watermark_cross` and `flip` both are 1, the watermark_crossed
169 // should remain 1. The event will be reported in this case.
170 1/1 watermark_crossed <= 1'b 1;
Tests: T18 T40 T51
171 1/1 end else if (active && flip) begin
Tests: T3 T5 T6
172 1/1 watermark_crossed <= 1'b 0;
Tests: T18 T40 T51
173 end
MISSING_ELSE
174 end
175
176 always_comb begin : watermark_event_logic
177 1/1 event_watermark_o = 1'b 0;
Tests: T1 T2 T3
178
179 1/1 if (active && watermark_cross) begin
Tests: T1 T2 T3
180 1/1 if (!watermark_crossed) begin
Tests: T18 T40 T51
181 1/1 event_watermark_o = 1'b 1;
Tests: T18 T40 T51
182 1/1 end else if (flip) begin
Tests: T18 T40 T51
183 // if flip is set and previous watermark_crossed is set, the event
184 // should be reported also. This means the host issues the next buffer
185 // address pointing above the threshold. This scenario, flip event and
186 // watermark event both should be reported.
187 0/1 ==> event_watermark_o = 1'b 1;
188 end
MISSING_ELSE
189 end
MISSING_ELSE
190 end : watermark_event_logic
191
192 ///////////////////
193 // State Machine //
194 ///////////////////
195 always_ff @(posedge clk_i or negedge rst_ni) begin
196 2/2 if (!rst_ni) st_q <= StIdle;
Tests: T1 T2 T3 | T1 T2 T3
197 1/1 else if (spi_mode_i != spi_device_pkg::FlashMode) begin
Tests: T3 T13 T15
198 1/1 st_q <= StIdle;
Tests: T3 T13 T15
199 end else begin
200 1/1 st_q <= st_d;
Tests: T18 T23 T40
201 end
202 end
203
204 always_comb begin
205 1/1 st_d = st_q;
Tests: T1 T2 T3
206
207 1/1 active = 1'b 0;
Tests: T1 T2 T3
208
209 1/1 unique case (st_q)
Tests: T1 T2 T3
210 StIdle: begin
211 1/1 if (start_i && (spi_mode_i == spi_device_pkg::FlashMode)
Tests: T1 T2 T3
212 && !sfdp_hit_i && !(mailbox_en_i && mailbox_hit_i)) begin
213 1/1 st_d = StActive;
Tests: T18 T40 T51
214
215 1/1 active = 1'b 1; // Assume address_update_i is high
Tests: T18 T40 T51
216 end
MISSING_ELSE
217 end
218
219 StActive: begin
220 // Deadend waiting CSb de-assertion
221 1/1 st_d = StActive;
Tests: T18 T40 T51
222
223 1/1 active = address_update_i;
Tests: T18 T40 T51
224 end
225
226 default: begin
227 st_d = StIdle;
Cond Coverage for Module :
spid_readbuffer
| Total | Covered | Percent |
|---|
| Conditions | 35 | 34 | 97.14 |
| Logical | 35 | 34 | 97.14 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 134
EXPRESSION (active && flip)
---1-- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T52,T53,T54 |
| 1 | 0 | Covered | T18,T40,T51 |
| 1 | 1 | Covered | T18,T40,T51 |
LINE 141
EXPRESSION (current_buffer_idx == next_buffer_addr)
--------------------1-------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T40,T51 |
LINE 156
EXPRESSION (active && flip && ((!flip_q)))
---1-- --2- -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T52,T53,T54 |
| 1 | 0 | 1 | Covered | T18,T40,T51 |
| 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | Covered | T18,T40,T51 |
LINE 159
EXPRESSION ((current_address_i[(spi_device_pkg::SramBufferAw - 1):0] >= threshold_i) && ((|threshold_i)))
------------------------------------1----------------------------------- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T13,T15 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T3,T15,T16 |
LINE 167
EXPRESSION (active && watermark_cross)
---1-- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T15,T16 |
| 1 | 0 | Covered | T18,T40,T51 |
| 1 | 1 | Covered | T18,T40,T51 |
LINE 171
EXPRESSION (active && flip)
---1-- --2-
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T52,T53,T54 |
| 1 | 0 | Covered | T18,T40,T51 |
| 1 | 1 | Covered | T18,T40,T51 |
LINE 179
EXPRESSION (active && watermark_cross)
---1-- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T15,T16 |
| 1 | 0 | Covered | T18,T40,T51 |
| 1 | 1 | Covered | T18,T40,T51 |
LINE 197
EXPRESSION (spi_mode_i != FlashMode)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T18,T23,T40 |
| 1 | Covered | T3,T13,T15 |
LINE 211
EXPRESSION (start_i && (spi_mode_i == FlashMode) && ((!sfdp_hit_i)) && ( ! (mailbox_en_i && mailbox_hit_i) ))
---1--- ------------2------------ -------3------- ------------------4------------------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T3,T15,T16 |
| 1 | 1 | 0 | 1 | Covered | T23,T55,T56 |
| 1 | 1 | 1 | 0 | Covered | T18,T23,T50 |
| 1 | 1 | 1 | 1 | Covered | T18,T40,T51 |
LINE 211
SUB-EXPRESSION (spi_mode_i == FlashMode)
------------1------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T3,T13,T15 |
| 1 | Covered | T1,T2,T3 |
LINE 211
SUB-EXPRESSION ( ! (mailbox_en_i && mailbox_hit_i) )
---------------1---------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T18,T23,T57 |
LINE 211
SUB-EXPRESSION (mailbox_en_i && mailbox_hit_i)
------1----- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T3,T13,T18 |
| 1 | 1 | Covered | T18,T23,T57 |
Branch Coverage for Module :
spid_readbuffer
| Line No. | Total | Covered | Percent |
| Branches |
|
28 |
21 |
75.00 |
| IF |
105 |
4 |
2 |
50.00 |
| IF |
130 |
4 |
3 |
75.00 |
| IF |
147 |
4 |
3 |
75.00 |
| IF |
163 |
5 |
4 |
80.00 |
| IF |
179 |
4 |
3 |
75.00 |
| IF |
196 |
3 |
3 |
100.00 |
| CASE |
209 |
4 |
3 |
75.00 |
105 if (!sys_rst_ni) begin
-1-
106 sys_clr_req <= 1'b0;
==>
107 end else if (sys_clr_i) begin
-2-
108 sys_clr_req <= 1'b1;
==>
109 end else if (sys_clr_ack) begin
-3-
110 sys_clr_req <= 1'b0;
==>
111 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Not Covered |
|
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
130 if (!sys_rst_ni) begin
-1-
131 next_buffer_addr <= (32-SramBufferAw)'(1); // pointing to next buffer
==>
132 end else if (spi_clr) begin
-2-
133 next_buffer_addr <= (32-SramBufferAw)'(1); // pointing to next buffer
==>
134 end else if (active && flip) begin
-3-
135 next_buffer_addr <= next_buffer_addr + 1'b 1;
==>
136 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T18,T40,T51 |
| 0 |
0 |
0 |
Covered |
T3,T5,T6 |
147 if (!sys_rst_ni) begin
-1-
148 flip_q <= 1'b 0;
==>
149 end else if (spi_clr) begin
-2-
150 flip_q <= 1'b 0;
==>
151 end else if (active) begin
-3-
152 flip_q <= flip;
==>
153 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Not Covered |
|
| 0 |
0 |
1 |
Covered |
T18,T40,T51 |
| 0 |
0 |
0 |
Covered |
T3,T5,T6 |
163 if (!sys_rst_ni) begin
-1-
164 watermark_crossed <= 1'b 0;
==>
165 end else if (spi_clr) begin
-2-
166 watermark_crossed <= 1'b 0;
==>
167 end else if (active && watermark_cross) begin
-3-
168 // When `watermark_cross` and `flip` both are 1, the watermark_crossed
169 // should remain 1. The event will be reported in this case.
170 watermark_crossed <= 1'b 1;
==>
171 end else if (active && flip) begin
-4-
172 watermark_crossed <= 1'b 0;
==>
173 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | -4- | Status | Tests |
| 1 |
- |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
- |
Not Covered |
|
| 0 |
0 |
1 |
- |
Covered |
T18,T40,T51 |
| 0 |
0 |
0 |
1 |
Covered |
T18,T40,T51 |
| 0 |
0 |
0 |
0 |
Covered |
T3,T5,T6 |
179 if (active && watermark_cross) begin
-1-
180 if (!watermark_crossed) begin
-2-
181 event_watermark_o = 1'b 1;
==>
182 end else if (flip) begin
-3-
183 // if flip is set and previous watermark_crossed is set, the event
184 // should be reported also. This means the host issues the next buffer
185 // address pointing above the threshold. This scenario, flip event and
186 // watermark event both should be reported.
187 event_watermark_o = 1'b 1;
==>
188 end
MISSING_ELSE
==>
189 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
1 |
- |
Covered |
T18,T40,T51 |
| 1 |
0 |
1 |
Not Covered |
|
| 1 |
0 |
0 |
Covered |
T18,T40,T51 |
| 0 |
- |
- |
Covered |
T1,T2,T3 |
196 if (!rst_ni) st_q <= StIdle;
-1-
==>
197 else if (spi_mode_i != spi_device_pkg::FlashMode) begin
-2-
198 st_q <= StIdle;
==>
199 end else begin
200 st_q <= st_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T3,T13,T15 |
| 0 |
0 |
Covered |
T18,T23,T40 |
209 unique case (st_q)
-1-
210 StIdle: begin
211 if (start_i && (spi_mode_i == spi_device_pkg::FlashMode)
-2-
212 && !sfdp_hit_i && !(mailbox_en_i && mailbox_hit_i)) begin
213 st_d = StActive;
==>
214
215 active = 1'b 1; // Assume address_update_i is high
216 end
MISSING_ELSE
==>
217 end
218
219 StActive: begin
220 // Deadend waiting CSb de-assertion
221 st_d = StActive;
==>
222
223 active = address_update_i;
224 end
225
226 default: begin
227 st_d = StIdle;
==>
Branches:
| -1- | -2- | Status | Tests |
| StIdle |
1 |
Covered |
T18,T40,T51 |
| StIdle |
0 |
Covered |
T1,T2,T3 |
| StActive |
- |
Covered |
T18,T40,T51 |
| default |
- |
Not Covered |
|
Assert Coverage for Module :
spid_readbuffer
Assertion Details
StartWithAddressUpdate_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
150126960 |
7727 |
0 |
0 |
| T3 |
57491 |
4 |
0 |
0 |
| T5 |
1008 |
0 |
0 |
0 |
| T6 |
59612 |
0 |
0 |
0 |
| T7 |
22059 |
0 |
0 |
0 |
| T9 |
91883 |
0 |
0 |
0 |
| T13 |
4208 |
0 |
0 |
0 |
| T14 |
864 |
0 |
0 |
0 |
| T15 |
13132 |
2 |
0 |
0 |
| T16 |
20820 |
4 |
0 |
0 |
| T17 |
4176 |
0 |
0 |
0 |
| T18 |
0 |
5 |
0 |
0 |
| T23 |
0 |
13 |
0 |
0 |
| T40 |
0 |
8 |
0 |
0 |
| T50 |
0 |
1 |
0 |
0 |
| T57 |
0 |
6 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
8 |
0 |
0 |
