Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
3476 |
0 |
0 |
T105 |
14641 |
203 |
0 |
0 |
T106 |
28199 |
2 |
0 |
0 |
T107 |
5851 |
12 |
0 |
0 |
T126 |
19283 |
236 |
0 |
0 |
T128 |
19092 |
249 |
0 |
0 |
T129 |
28512 |
3 |
0 |
0 |
T133 |
12739 |
158 |
0 |
0 |
T138 |
8104 |
1 |
0 |
0 |
T143 |
8794 |
6 |
0 |
0 |
T144 |
5412 |
2 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2276 |
0 |
0 |
T127 |
34001 |
26 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
266 |
0 |
0 |
T173 |
20661 |
45 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
5 |
0 |
0 |
T179 |
38012 |
251 |
0 |
0 |
T180 |
6822 |
8 |
0 |
0 |
T181 |
14551 |
35 |
0 |
0 |
T182 |
78682 |
143 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2381 |
0 |
0 |
T127 |
34001 |
38 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
247 |
0 |
0 |
T173 |
20661 |
80 |
0 |
0 |
T177 |
3809 |
6 |
0 |
0 |
T178 |
7369 |
8 |
0 |
0 |
T179 |
38012 |
280 |
0 |
0 |
T180 |
6822 |
5 |
0 |
0 |
T181 |
14551 |
18 |
0 |
0 |
T182 |
78682 |
122 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2553 |
0 |
0 |
T127 |
34001 |
51 |
0 |
0 |
T144 |
5412 |
13 |
0 |
0 |
T150 |
70601 |
282 |
0 |
0 |
T173 |
20661 |
78 |
0 |
0 |
T177 |
3809 |
13 |
0 |
0 |
T178 |
7369 |
8 |
0 |
0 |
T179 |
38012 |
248 |
0 |
0 |
T180 |
6822 |
15 |
0 |
0 |
T181 |
14551 |
43 |
0 |
0 |
T182 |
78682 |
157 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
8184 |
0 |
0 |
T105 |
14641 |
2 |
0 |
0 |
T127 |
34001 |
431 |
0 |
0 |
T144 |
5412 |
8 |
0 |
0 |
T150 |
70601 |
216 |
0 |
0 |
T173 |
20661 |
77 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
107 |
0 |
0 |
T179 |
38012 |
228 |
0 |
0 |
T180 |
6822 |
10 |
0 |
0 |
T181 |
14551 |
280 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
8596 |
0 |
0 |
T127 |
34001 |
290 |
0 |
0 |
T144 |
5412 |
122 |
0 |
0 |
T150 |
70601 |
280 |
0 |
0 |
T173 |
20661 |
85 |
0 |
0 |
T177 |
3809 |
3 |
0 |
0 |
T178 |
7369 |
135 |
0 |
0 |
T179 |
38012 |
243 |
0 |
0 |
T180 |
6822 |
3 |
0 |
0 |
T181 |
14551 |
287 |
0 |
0 |
T182 |
78682 |
168 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
8077 |
0 |
0 |
T127 |
34001 |
654 |
0 |
0 |
T144 |
5412 |
14 |
0 |
0 |
T150 |
70601 |
260 |
0 |
0 |
T173 |
20661 |
53 |
0 |
0 |
T177 |
3809 |
125 |
0 |
0 |
T178 |
7369 |
102 |
0 |
0 |
T179 |
38012 |
243 |
0 |
0 |
T180 |
6822 |
8 |
0 |
0 |
T181 |
14551 |
290 |
0 |
0 |
T182 |
78682 |
118 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
7968 |
0 |
0 |
T127 |
34001 |
640 |
0 |
0 |
T144 |
5412 |
130 |
0 |
0 |
T150 |
70601 |
309 |
0 |
0 |
T173 |
20661 |
55 |
0 |
0 |
T177 |
3809 |
152 |
0 |
0 |
T178 |
7369 |
220 |
0 |
0 |
T179 |
38012 |
219 |
0 |
0 |
T180 |
6822 |
9 |
0 |
0 |
T181 |
14551 |
147 |
0 |
0 |
T182 |
78682 |
148 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
7400 |
0 |
0 |
T105 |
14641 |
6 |
0 |
0 |
T127 |
34001 |
149 |
0 |
0 |
T144 |
5412 |
137 |
0 |
0 |
T150 |
70601 |
325 |
0 |
0 |
T173 |
20661 |
88 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
218 |
0 |
0 |
T179 |
38012 |
221 |
0 |
0 |
T180 |
6822 |
22 |
0 |
0 |
T181 |
14551 |
166 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
9574 |
0 |
0 |
T127 |
34001 |
1061 |
0 |
0 |
T144 |
5412 |
113 |
0 |
0 |
T150 |
70601 |
331 |
0 |
0 |
T173 |
20661 |
94 |
0 |
0 |
T177 |
3809 |
6 |
0 |
0 |
T178 |
7369 |
120 |
0 |
0 |
T179 |
38012 |
242 |
0 |
0 |
T180 |
6822 |
33 |
0 |
0 |
T181 |
14551 |
160 |
0 |
0 |
T182 |
78682 |
164 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
9165 |
0 |
0 |
T127 |
34001 |
766 |
0 |
0 |
T144 |
5412 |
12 |
0 |
0 |
T150 |
70601 |
237 |
0 |
0 |
T173 |
20661 |
72 |
0 |
0 |
T177 |
3809 |
141 |
0 |
0 |
T178 |
7369 |
102 |
0 |
0 |
T179 |
38012 |
217 |
0 |
0 |
T180 |
6822 |
10 |
0 |
0 |
T181 |
14551 |
283 |
0 |
0 |
T182 |
78682 |
113 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
8955 |
0 |
0 |
T127 |
34001 |
705 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
291 |
0 |
0 |
T173 |
20661 |
33 |
0 |
0 |
T177 |
3809 |
119 |
0 |
0 |
T178 |
7369 |
131 |
0 |
0 |
T179 |
38012 |
235 |
0 |
0 |
T180 |
6822 |
9 |
0 |
0 |
T181 |
14551 |
156 |
0 |
0 |
T182 |
78682 |
124 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4606 |
0 |
0 |
T127 |
34001 |
497 |
0 |
0 |
T144 |
5412 |
40 |
0 |
0 |
T150 |
70601 |
291 |
0 |
0 |
T173 |
20661 |
91 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
58 |
0 |
0 |
T179 |
38012 |
204 |
0 |
0 |
T180 |
6822 |
14 |
0 |
0 |
T181 |
14551 |
20 |
0 |
0 |
T182 |
78682 |
127 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4425 |
0 |
0 |
T127 |
34001 |
267 |
0 |
0 |
T144 |
5412 |
10 |
0 |
0 |
T150 |
70601 |
318 |
0 |
0 |
T173 |
20661 |
68 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
20 |
0 |
0 |
T179 |
38012 |
273 |
0 |
0 |
T181 |
14551 |
52 |
0 |
0 |
T182 |
78682 |
198 |
0 |
0 |
T183 |
19813 |
42 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4437 |
0 |
0 |
T127 |
34001 |
217 |
0 |
0 |
T144 |
5412 |
2 |
0 |
0 |
T150 |
70601 |
245 |
0 |
0 |
T173 |
20661 |
102 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
56 |
0 |
0 |
T179 |
38012 |
282 |
0 |
0 |
T180 |
6822 |
19 |
0 |
0 |
T181 |
14551 |
49 |
0 |
0 |
T182 |
78682 |
151 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4192 |
0 |
0 |
T127 |
34001 |
212 |
0 |
0 |
T144 |
5412 |
10 |
0 |
0 |
T150 |
70601 |
294 |
0 |
0 |
T173 |
20661 |
72 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
65 |
0 |
0 |
T179 |
38012 |
226 |
0 |
0 |
T180 |
6822 |
19 |
0 |
0 |
T181 |
14551 |
26 |
0 |
0 |
T182 |
78682 |
129 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4604 |
0 |
0 |
T127 |
34001 |
302 |
0 |
0 |
T144 |
5412 |
4 |
0 |
0 |
T150 |
70601 |
264 |
0 |
0 |
T173 |
20661 |
110 |
0 |
0 |
T177 |
3809 |
61 |
0 |
0 |
T178 |
7369 |
73 |
0 |
0 |
T179 |
38012 |
224 |
0 |
0 |
T180 |
6822 |
10 |
0 |
0 |
T181 |
14551 |
64 |
0 |
0 |
T182 |
78682 |
125 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4843 |
0 |
0 |
T127 |
34001 |
273 |
0 |
0 |
T144 |
5412 |
60 |
0 |
0 |
T150 |
70601 |
301 |
0 |
0 |
T173 |
20661 |
105 |
0 |
0 |
T177 |
3809 |
58 |
0 |
0 |
T178 |
7369 |
6 |
0 |
0 |
T179 |
38012 |
194 |
0 |
0 |
T180 |
6822 |
15 |
0 |
0 |
T181 |
14551 |
73 |
0 |
0 |
T182 |
78682 |
116 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4726 |
0 |
0 |
T127 |
34001 |
359 |
0 |
0 |
T144 |
5412 |
45 |
0 |
0 |
T150 |
70601 |
282 |
0 |
0 |
T173 |
20661 |
51 |
0 |
0 |
T177 |
3809 |
9 |
0 |
0 |
T178 |
7369 |
108 |
0 |
0 |
T179 |
38012 |
255 |
0 |
0 |
T180 |
6822 |
28 |
0 |
0 |
T181 |
14551 |
123 |
0 |
0 |
T182 |
78682 |
138 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4651 |
0 |
0 |
T127 |
34001 |
395 |
0 |
0 |
T134 |
11269 |
1 |
0 |
0 |
T144 |
5412 |
8 |
0 |
0 |
T150 |
70601 |
307 |
0 |
0 |
T173 |
20661 |
84 |
0 |
0 |
T178 |
7369 |
7 |
0 |
0 |
T179 |
38012 |
210 |
0 |
0 |
T180 |
6822 |
14 |
0 |
0 |
T181 |
14551 |
107 |
0 |
0 |
T182 |
78682 |
69 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4616 |
0 |
0 |
T127 |
34001 |
294 |
0 |
0 |
T144 |
5412 |
62 |
0 |
0 |
T150 |
70601 |
269 |
0 |
0 |
T173 |
20661 |
66 |
0 |
0 |
T177 |
3809 |
51 |
0 |
0 |
T178 |
7369 |
58 |
0 |
0 |
T179 |
38012 |
208 |
0 |
0 |
T180 |
6822 |
7 |
0 |
0 |
T181 |
14551 |
130 |
0 |
0 |
T182 |
78682 |
139 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4558 |
0 |
0 |
T127 |
34001 |
370 |
0 |
0 |
T144 |
5412 |
15 |
0 |
0 |
T150 |
70601 |
292 |
0 |
0 |
T173 |
20661 |
80 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
55 |
0 |
0 |
T179 |
38012 |
288 |
0 |
0 |
T180 |
6822 |
4 |
0 |
0 |
T181 |
14551 |
81 |
0 |
0 |
T182 |
78682 |
166 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4644 |
0 |
0 |
T127 |
34001 |
324 |
0 |
0 |
T144 |
5412 |
2 |
0 |
0 |
T150 |
70601 |
294 |
0 |
0 |
T173 |
20661 |
32 |
0 |
0 |
T177 |
3809 |
2 |
0 |
0 |
T178 |
7369 |
59 |
0 |
0 |
T179 |
38012 |
213 |
0 |
0 |
T180 |
6822 |
3 |
0 |
0 |
T181 |
14551 |
102 |
0 |
0 |
T182 |
78682 |
136 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4465 |
0 |
0 |
T127 |
34001 |
195 |
0 |
0 |
T144 |
5412 |
66 |
0 |
0 |
T150 |
70601 |
273 |
0 |
0 |
T173 |
20661 |
80 |
0 |
0 |
T177 |
3809 |
6 |
0 |
0 |
T178 |
7369 |
8 |
0 |
0 |
T179 |
38012 |
227 |
0 |
0 |
T180 |
6822 |
7 |
0 |
0 |
T181 |
14551 |
125 |
0 |
0 |
T182 |
78682 |
117 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4559 |
0 |
0 |
T127 |
34001 |
275 |
0 |
0 |
T128 |
19092 |
6 |
0 |
0 |
T144 |
5412 |
3 |
0 |
0 |
T150 |
70601 |
279 |
0 |
0 |
T173 |
20661 |
58 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
51 |
0 |
0 |
T179 |
38012 |
233 |
0 |
0 |
T180 |
6822 |
29 |
0 |
0 |
T181 |
14551 |
97 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4370 |
0 |
0 |
T127 |
34001 |
315 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
242 |
0 |
0 |
T173 |
20661 |
70 |
0 |
0 |
T177 |
3809 |
55 |
0 |
0 |
T178 |
7369 |
55 |
0 |
0 |
T179 |
38012 |
233 |
0 |
0 |
T180 |
6822 |
5 |
0 |
0 |
T181 |
14551 |
54 |
0 |
0 |
T182 |
78682 |
172 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4656 |
0 |
0 |
T127 |
34001 |
397 |
0 |
0 |
T144 |
5412 |
45 |
0 |
0 |
T150 |
70601 |
302 |
0 |
0 |
T173 |
20661 |
48 |
0 |
0 |
T177 |
3809 |
6 |
0 |
0 |
T178 |
7369 |
111 |
0 |
0 |
T179 |
38012 |
241 |
0 |
0 |
T180 |
6822 |
7 |
0 |
0 |
T181 |
14551 |
108 |
0 |
0 |
T182 |
78682 |
155 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4665 |
0 |
0 |
T127 |
34001 |
207 |
0 |
0 |
T144 |
5412 |
2 |
0 |
0 |
T150 |
70601 |
251 |
0 |
0 |
T173 |
20661 |
74 |
0 |
0 |
T177 |
3809 |
50 |
0 |
0 |
T178 |
7369 |
49 |
0 |
0 |
T179 |
38012 |
285 |
0 |
0 |
T180 |
6822 |
24 |
0 |
0 |
T181 |
14551 |
128 |
0 |
0 |
T182 |
78682 |
150 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4250 |
0 |
0 |
T127 |
34001 |
230 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
286 |
0 |
0 |
T173 |
20661 |
42 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
6 |
0 |
0 |
T179 |
38012 |
250 |
0 |
0 |
T180 |
6822 |
21 |
0 |
0 |
T181 |
14551 |
147 |
0 |
0 |
T182 |
78682 |
138 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4264 |
0 |
0 |
T127 |
34001 |
377 |
0 |
0 |
T144 |
5412 |
4 |
0 |
0 |
T150 |
70601 |
308 |
0 |
0 |
T173 |
20661 |
31 |
0 |
0 |
T178 |
7369 |
50 |
0 |
0 |
T179 |
38012 |
241 |
0 |
0 |
T180 |
6822 |
12 |
0 |
0 |
T181 |
14551 |
118 |
0 |
0 |
T182 |
78682 |
126 |
0 |
0 |
T183 |
19813 |
131 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4203 |
0 |
0 |
T127 |
34001 |
304 |
0 |
0 |
T144 |
5412 |
10 |
0 |
0 |
T150 |
70601 |
265 |
0 |
0 |
T173 |
20661 |
33 |
0 |
0 |
T177 |
3809 |
9 |
0 |
0 |
T178 |
7369 |
68 |
0 |
0 |
T179 |
38012 |
256 |
0 |
0 |
T180 |
6822 |
20 |
0 |
0 |
T181 |
14551 |
58 |
0 |
0 |
T182 |
78682 |
135 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4649 |
0 |
0 |
T127 |
34001 |
264 |
0 |
0 |
T144 |
5412 |
41 |
0 |
0 |
T150 |
70601 |
256 |
0 |
0 |
T173 |
20661 |
28 |
0 |
0 |
T177 |
3809 |
43 |
0 |
0 |
T178 |
7369 |
69 |
0 |
0 |
T179 |
38012 |
248 |
0 |
0 |
T180 |
6822 |
8 |
0 |
0 |
T181 |
14551 |
137 |
0 |
0 |
T182 |
78682 |
164 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4307 |
0 |
0 |
T127 |
34001 |
179 |
0 |
0 |
T144 |
5412 |
31 |
0 |
0 |
T150 |
70601 |
288 |
0 |
0 |
T173 |
20661 |
44 |
0 |
0 |
T177 |
3809 |
57 |
0 |
0 |
T179 |
38012 |
255 |
0 |
0 |
T180 |
6822 |
6 |
0 |
0 |
T181 |
14551 |
121 |
0 |
0 |
T182 |
78682 |
122 |
0 |
0 |
T183 |
19813 |
73 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4107 |
0 |
0 |
T127 |
34001 |
187 |
0 |
0 |
T144 |
5412 |
11 |
0 |
0 |
T150 |
70601 |
281 |
0 |
0 |
T173 |
20661 |
80 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
67 |
0 |
0 |
T179 |
38012 |
244 |
0 |
0 |
T181 |
14551 |
112 |
0 |
0 |
T182 |
78682 |
137 |
0 |
0 |
T183 |
19813 |
50 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
5104 |
0 |
0 |
T127 |
34001 |
380 |
0 |
0 |
T139 |
14659 |
5 |
0 |
0 |
T144 |
5412 |
4 |
0 |
0 |
T150 |
70601 |
273 |
0 |
0 |
T173 |
20661 |
84 |
0 |
0 |
T177 |
3809 |
48 |
0 |
0 |
T178 |
7369 |
49 |
0 |
0 |
T179 |
38012 |
214 |
0 |
0 |
T180 |
6822 |
18 |
0 |
0 |
T181 |
14551 |
75 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4595 |
0 |
0 |
T127 |
34001 |
246 |
0 |
0 |
T139 |
14659 |
6 |
0 |
0 |
T144 |
5412 |
48 |
0 |
0 |
T150 |
70601 |
308 |
0 |
0 |
T173 |
20661 |
73 |
0 |
0 |
T178 |
7369 |
90 |
0 |
0 |
T179 |
38012 |
236 |
0 |
0 |
T180 |
6822 |
23 |
0 |
0 |
T181 |
14551 |
75 |
0 |
0 |
T182 |
78682 |
115 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2402 |
0 |
0 |
T127 |
34001 |
71 |
0 |
0 |
T128 |
19092 |
3 |
0 |
0 |
T144 |
5412 |
8 |
0 |
0 |
T150 |
70601 |
273 |
0 |
0 |
T173 |
20661 |
74 |
0 |
0 |
T177 |
3809 |
7 |
0 |
0 |
T178 |
7369 |
13 |
0 |
0 |
T179 |
38012 |
230 |
0 |
0 |
T180 |
6822 |
15 |
0 |
0 |
T181 |
14551 |
32 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2377 |
0 |
0 |
T127 |
34001 |
60 |
0 |
0 |
T144 |
5412 |
11 |
0 |
0 |
T150 |
70601 |
221 |
0 |
0 |
T173 |
20661 |
34 |
0 |
0 |
T177 |
3809 |
9 |
0 |
0 |
T178 |
7369 |
2 |
0 |
0 |
T179 |
38012 |
290 |
0 |
0 |
T180 |
6822 |
5 |
0 |
0 |
T181 |
14551 |
17 |
0 |
0 |
T182 |
78682 |
119 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2455 |
0 |
0 |
T127 |
34001 |
90 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
283 |
0 |
0 |
T173 |
20661 |
96 |
0 |
0 |
T177 |
3809 |
2 |
0 |
0 |
T178 |
7369 |
12 |
0 |
0 |
T179 |
38012 |
259 |
0 |
0 |
T180 |
6822 |
3 |
0 |
0 |
T181 |
14551 |
41 |
0 |
0 |
T182 |
78682 |
121 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2343 |
0 |
0 |
T127 |
34001 |
50 |
0 |
0 |
T144 |
5412 |
7 |
0 |
0 |
T150 |
70601 |
297 |
0 |
0 |
T173 |
20661 |
57 |
0 |
0 |
T177 |
3809 |
12 |
0 |
0 |
T178 |
7369 |
9 |
0 |
0 |
T179 |
38012 |
232 |
0 |
0 |
T180 |
6822 |
1 |
0 |
0 |
T181 |
14551 |
23 |
0 |
0 |
T182 |
78682 |
127 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2383 |
0 |
0 |
T127 |
34001 |
69 |
0 |
0 |
T144 |
5412 |
10 |
0 |
0 |
T150 |
70601 |
182 |
0 |
0 |
T173 |
20661 |
91 |
0 |
0 |
T177 |
3809 |
10 |
0 |
0 |
T178 |
7369 |
13 |
0 |
0 |
T179 |
38012 |
187 |
0 |
0 |
T180 |
6822 |
10 |
0 |
0 |
T181 |
14551 |
53 |
0 |
0 |
T182 |
78682 |
157 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
4122 |
0 |
0 |
T99 |
777903 |
46 |
0 |
0 |
T168 |
0 |
34 |
0 |
0 |
T171 |
0 |
8 |
0 |
0 |
T184 |
0 |
66 |
0 |
0 |
T185 |
0 |
10 |
0 |
0 |
T186 |
0 |
32 |
0 |
0 |
T187 |
0 |
14 |
0 |
0 |
T188 |
0 |
28 |
0 |
0 |
T189 |
0 |
31 |
0 |
0 |
T190 |
0 |
14 |
0 |
0 |
T191 |
70461 |
0 |
0 |
0 |
T192 |
948 |
0 |
0 |
0 |
T193 |
133226 |
0 |
0 |
0 |
T194 |
74433 |
0 |
0 |
0 |
T195 |
15804 |
0 |
0 |
0 |
T196 |
1319 |
0 |
0 |
0 |
T197 |
105175 |
0 |
0 |
0 |
T198 |
1273 |
0 |
0 |
0 |
T199 |
133779 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2377 |
0 |
0 |
T127 |
34001 |
65 |
0 |
0 |
T144 |
5412 |
1 |
0 |
0 |
T150 |
70601 |
290 |
0 |
0 |
T173 |
20661 |
58 |
0 |
0 |
T177 |
3809 |
6 |
0 |
0 |
T178 |
7369 |
17 |
0 |
0 |
T179 |
38012 |
224 |
0 |
0 |
T180 |
6822 |
7 |
0 |
0 |
T181 |
14551 |
22 |
0 |
0 |
T182 |
78682 |
116 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2346 |
0 |
0 |
T127 |
34001 |
59 |
0 |
0 |
T144 |
5412 |
18 |
0 |
0 |
T150 |
70601 |
240 |
0 |
0 |
T173 |
20661 |
104 |
0 |
0 |
T177 |
3809 |
6 |
0 |
0 |
T178 |
7369 |
2 |
0 |
0 |
T179 |
38012 |
231 |
0 |
0 |
T181 |
14551 |
45 |
0 |
0 |
T182 |
78682 |
125 |
0 |
0 |
T183 |
19813 |
66 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2308 |
0 |
0 |
T105 |
14641 |
2 |
0 |
0 |
T127 |
34001 |
55 |
0 |
0 |
T144 |
5412 |
8 |
0 |
0 |
T150 |
70601 |
234 |
0 |
0 |
T173 |
20661 |
139 |
0 |
0 |
T177 |
3809 |
2 |
0 |
0 |
T178 |
7369 |
12 |
0 |
0 |
T179 |
38012 |
201 |
0 |
0 |
T180 |
6822 |
8 |
0 |
0 |
T181 |
14551 |
27 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2351 |
0 |
0 |
T127 |
34001 |
47 |
0 |
0 |
T134 |
11269 |
4 |
0 |
0 |
T144 |
5412 |
15 |
0 |
0 |
T150 |
70601 |
263 |
0 |
0 |
T173 |
20661 |
98 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
3 |
0 |
0 |
T179 |
38012 |
252 |
0 |
0 |
T180 |
6822 |
15 |
0 |
0 |
T181 |
14551 |
18 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2063 |
0 |
0 |
T127 |
34001 |
48 |
0 |
0 |
T144 |
5412 |
16 |
0 |
0 |
T150 |
70601 |
296 |
0 |
0 |
T173 |
20661 |
48 |
0 |
0 |
T177 |
3809 |
5 |
0 |
0 |
T178 |
7369 |
4 |
0 |
0 |
T179 |
38012 |
204 |
0 |
0 |
T180 |
6822 |
3 |
0 |
0 |
T181 |
14551 |
28 |
0 |
0 |
T182 |
78682 |
130 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2251 |
0 |
0 |
T105 |
14641 |
7 |
0 |
0 |
T127 |
34001 |
59 |
0 |
0 |
T144 |
5412 |
6 |
0 |
0 |
T150 |
70601 |
211 |
0 |
0 |
T173 |
20661 |
76 |
0 |
0 |
T178 |
7369 |
11 |
0 |
0 |
T179 |
38012 |
244 |
0 |
0 |
T180 |
6822 |
4 |
0 |
0 |
T181 |
14551 |
17 |
0 |
0 |
T182 |
78682 |
133 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2939 |
0 |
0 |
T127 |
34001 |
133 |
0 |
0 |
T144 |
5412 |
5 |
0 |
0 |
T150 |
70601 |
286 |
0 |
0 |
T173 |
20661 |
115 |
0 |
0 |
T177 |
3809 |
11 |
0 |
0 |
T178 |
7369 |
9 |
0 |
0 |
T179 |
38012 |
229 |
0 |
0 |
T180 |
6822 |
7 |
0 |
0 |
T181 |
14551 |
28 |
0 |
0 |
T182 |
78682 |
150 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2166 |
0 |
0 |
T105 |
14641 |
1 |
0 |
0 |
T127 |
34001 |
32 |
0 |
0 |
T144 |
5412 |
6 |
0 |
0 |
T150 |
70601 |
257 |
0 |
0 |
T173 |
20661 |
63 |
0 |
0 |
T178 |
7369 |
12 |
0 |
0 |
T179 |
38012 |
193 |
0 |
0 |
T180 |
6822 |
1 |
0 |
0 |
T181 |
14551 |
29 |
0 |
0 |
T182 |
78682 |
126 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2985 |
0 |
0 |
T105 |
14641 |
6 |
0 |
0 |
T127 |
34001 |
155 |
0 |
0 |
T128 |
19092 |
3 |
0 |
0 |
T144 |
5412 |
17 |
0 |
0 |
T150 |
70601 |
283 |
0 |
0 |
T173 |
20661 |
62 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
10 |
0 |
0 |
T179 |
38012 |
233 |
0 |
0 |
T180 |
6822 |
12 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2542 |
0 |
0 |
T127 |
34001 |
71 |
0 |
0 |
T150 |
70601 |
280 |
0 |
0 |
T173 |
20661 |
138 |
0 |
0 |
T177 |
3809 |
12 |
0 |
0 |
T178 |
7369 |
10 |
0 |
0 |
T179 |
38012 |
246 |
0 |
0 |
T180 |
6822 |
14 |
0 |
0 |
T181 |
14551 |
27 |
0 |
0 |
T182 |
78682 |
116 |
0 |
0 |
T183 |
19813 |
76 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2056 |
0 |
0 |
T127 |
34001 |
30 |
0 |
0 |
T144 |
5412 |
15 |
0 |
0 |
T150 |
70601 |
274 |
0 |
0 |
T173 |
20661 |
109 |
0 |
0 |
T177 |
3809 |
10 |
0 |
0 |
T178 |
7369 |
9 |
0 |
0 |
T179 |
38012 |
218 |
0 |
0 |
T180 |
6822 |
7 |
0 |
0 |
T181 |
14551 |
21 |
0 |
0 |
T182 |
78682 |
100 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2251 |
0 |
0 |
T127 |
34001 |
32 |
0 |
0 |
T144 |
5412 |
12 |
0 |
0 |
T150 |
70601 |
301 |
0 |
0 |
T173 |
20661 |
42 |
0 |
0 |
T177 |
3809 |
1 |
0 |
0 |
T179 |
38012 |
196 |
0 |
0 |
T181 |
14551 |
23 |
0 |
0 |
T182 |
78682 |
171 |
0 |
0 |
T183 |
19813 |
72 |
0 |
0 |
T200 |
11261 |
8 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2256 |
0 |
0 |
T127 |
34001 |
50 |
0 |
0 |
T144 |
5412 |
2 |
0 |
0 |
T150 |
70601 |
296 |
0 |
0 |
T173 |
20661 |
81 |
0 |
0 |
T177 |
3809 |
1 |
0 |
0 |
T178 |
7369 |
9 |
0 |
0 |
T179 |
38012 |
245 |
0 |
0 |
T180 |
6822 |
15 |
0 |
0 |
T181 |
14551 |
12 |
0 |
0 |
T182 |
78682 |
129 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2318 |
0 |
0 |
T127 |
34001 |
32 |
0 |
0 |
T144 |
5412 |
10 |
0 |
0 |
T150 |
70601 |
201 |
0 |
0 |
T173 |
20661 |
114 |
0 |
0 |
T177 |
3809 |
9 |
0 |
0 |
T178 |
7369 |
4 |
0 |
0 |
T179 |
38012 |
249 |
0 |
0 |
T180 |
6822 |
6 |
0 |
0 |
T181 |
14551 |
27 |
0 |
0 |
T182 |
78682 |
152 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2351 |
0 |
0 |
T127 |
34001 |
37 |
0 |
0 |
T144 |
5412 |
8 |
0 |
0 |
T150 |
70601 |
290 |
0 |
0 |
T173 |
20661 |
102 |
0 |
0 |
T178 |
7369 |
2 |
0 |
0 |
T179 |
38012 |
250 |
0 |
0 |
T181 |
14551 |
17 |
0 |
0 |
T182 |
78682 |
127 |
0 |
0 |
T183 |
19813 |
80 |
0 |
0 |
T200 |
11261 |
12 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
490607002 |
2224 |
0 |
0 |
T127 |
34001 |
42 |
0 |
0 |
T144 |
5412 |
1 |
0 |
0 |
T150 |
70601 |
272 |
0 |
0 |
T173 |
20661 |
43 |
0 |
0 |
T177 |
3809 |
4 |
0 |
0 |
T178 |
7369 |
9 |
0 |
0 |
T179 |
38012 |
227 |
0 |
0 |
T180 |
6822 |
27 |
0 |
0 |
T181 |
14551 |
20 |
0 |
0 |
T182 |
78682 |
123 |
0 |
0 |