Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2542175	1			T1	1		T2	1		T3	1
all_values[1]	2542175	1			T1	1		T2	1		T3	1
all_values[2]	2542175	1			T1	1		T2	1		T3	1
all_values[3]	2542175	1			T1	1		T2	1		T3	1
all_values[4]	2542175	1			T1	1		T2	1		T3	1
all_values[5]	2542175	1			T1	1		T2	1		T3	1
all_values[6]	2542175	1			T1	1		T2	1		T3	1
all_values[7]	2542175	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20105366

1

T1

8

T2

8

T3

8

auto[1]

232034

1

T41

41

T24

47

T35

119

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20310040

1

T1

8

T2

8

T3

8

auto[1]

27360

1

T32

261

T41

41

T24

38

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2485628	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	12298	1			T32	109		T41	2		T24	5
all_values[0]	auto[1]	auto[0]	43501	1			T41	4		T24	1		T35	8
all_values[0]	auto[1]	auto[1]	748	1			T24	3		T35	2		T36	68
all_values[1]	auto[0]	auto[0]	2488294	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	8613	1			T32	109		T41	1		T24	2
all_values[1]	auto[1]	auto[0]	44882	1			T41	3		T24	4		T35	9
all_values[1]	auto[1]	auto[1]	386	1			T41	6		T24	2		T35	5
all_values[2]	auto[0]	auto[0]	2492865	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	3016	1			T32	43		T41	4		T24	5
all_values[2]	auto[1]	auto[0]	46040	1			T41	1		T24	3		T35	13
all_values[2]	auto[1]	auto[1]	254	1			T41	1		T35	3		T36	4
all_values[3]	auto[0]	auto[0]	2537493	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	231	1			T41	2		T24	3		T35	7
all_values[3]	auto[1]	auto[0]	4253	1			T41	3		T24	3		T35	10
all_values[3]	auto[1]	auto[1]	198	1			T41	3		T24	5		T35	7
all_values[4]	auto[0]	auto[0]	2525581	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	254	1			T41	5		T24	2		T35	4
all_values[4]	auto[1]	auto[0]	16154	1			T24	5		T35	8		T36	2317
all_values[4]	auto[1]	auto[1]	186	1			T41	2		T24	1		T35	12
all_values[5]	auto[0]	auto[0]	2526043	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	188	1			T41	3		T24	2		T35	8
all_values[5]	auto[1]	auto[0]	15769	1			T41	1		T24	6		T35	4
all_values[5]	auto[1]	auto[1]	175	1			T41	2		T24	2		T35	6
all_values[6]	auto[0]	auto[0]	2531412	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	203	1			T24	2		T35	5		T36	4
all_values[6]	auto[1]	auto[0]	10348	1			T41	5		T24	2		T35	9
all_values[6]	auto[1]	auto[1]	212	1			T41	4		T24	2		T35	5
all_values[7]	auto[0]	auto[0]	2493042	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	205	1			T41	3		T24	2		T35	3
all_values[7]	auto[1]	auto[0]	48735	1			T41	3		T24	8		T35	13
all_values[7]	auto[1]	auto[1]	193	1			T41	3		T35	5		T36	3