Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total tests in report: 1129
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
60.63 60.63 92.31 92.31 78.85 78.85 64.27 64.27 17.78 17.78 89.09 89.09 71.69 71.69 10.40 10.40 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1341566798
74.51 13.88 96.40 4.10 88.72 9.87 69.78 5.51 57.78 40.00 94.62 5.53 83.78 12.09 30.45 20.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1580038918
79.83 5.32 96.94 0.54 89.67 0.95 87.80 18.01 71.11 13.33 95.23 0.61 83.93 0.14 34.11 3.66 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.1890158568
84.15 4.33 97.24 0.30 90.30 0.63 87.89 0.10 86.67 15.56 95.77 0.54 84.07 0.14 47.13 13.02 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1152486608
87.34 3.19 97.72 0.48 91.66 1.36 90.16 2.26 91.11 4.44 96.30 0.52 84.35 0.28 60.10 12.97 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1877708246
89.04 1.70 97.74 0.02 91.82 0.16 91.54 1.38 91.11 0.00 96.33 0.03 92.89 8.53 61.88 1.78 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3925008244
90.32 1.28 97.99 0.25 92.25 0.44 92.13 0.59 93.33 2.22 96.70 0.37 93.46 0.57 66.39 4.50 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.294714136
91.30 0.98 97.99 0.00 92.26 0.01 92.13 0.00 93.33 0.00 96.70 0.00 93.46 0.00 73.22 6.83 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3610434588
91.98 0.68 98.01 0.02 92.26 0.00 96.85 4.72 93.33 0.00 96.70 0.00 93.46 0.00 73.22 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.130786717
92.49 0.51 98.01 0.00 92.26 0.00 96.85 0.00 93.33 0.00 96.70 0.00 93.46 0.00 76.78 3.56 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.334087790
92.89 0.40 98.03 0.02 92.29 0.02 96.85 0.00 93.33 0.00 96.70 0.00 93.46 0.00 79.55 2.77 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.520385205
93.25 0.36 98.06 0.03 92.33 0.04 96.85 0.00 93.33 0.00 96.77 0.07 93.46 0.00 81.93 2.38 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2366505287
93.56 0.31 98.06 0.00 92.33 0.00 96.85 0.00 93.33 0.00 96.77 0.00 93.60 0.14 83.96 2.03 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3146017565
93.82 0.26 98.06 0.00 93.21 0.88 96.85 0.00 93.33 0.00 96.80 0.03 93.74 0.14 84.75 0.79 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.621933937
94.08 0.26 98.06 0.00 93.23 0.02 98.23 1.38 93.33 0.00 96.80 0.00 93.88 0.14 85.00 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1527587387
94.32 0.24 98.06 0.00 93.23 0.00 98.23 0.00 93.33 0.00 96.80 0.00 93.88 0.00 86.68 1.68 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.886582395
94.53 0.21 98.17 0.11 93.57 0.34 98.23 0.00 93.33 0.00 96.96 0.15 94.45 0.57 86.98 0.30 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3380671242
94.72 0.19 98.17 0.00 93.57 0.00 98.23 0.00 93.33 0.00 96.96 0.00 94.45 0.00 88.32 1.34 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1252768607
94.91 0.19 98.17 0.00 93.57 0.00 98.23 0.00 93.33 0.00 96.96 0.00 94.45 0.00 89.65 1.34 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.666875822
95.06 0.15 98.17 0.00 93.57 0.00 98.23 0.00 93.33 0.00 96.96 0.00 94.45 0.00 90.69 1.04 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1366748242
95.20 0.14 98.17 0.00 93.57 0.00 98.23 0.00 93.33 0.00 96.96 0.00 95.45 1.00 90.69 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3732304022
95.33 0.13 98.17 0.00 93.57 0.00 98.23 0.00 93.33 0.00 96.96 0.00 95.45 0.00 91.63 0.94 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2625586870
95.47 0.13 98.17 0.00 93.57 0.00 98.23 0.00 93.33 0.00 96.96 0.00 95.45 0.00 92.57 0.94 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1188636917
95.58 0.11 98.23 0.06 93.61 0.04 98.23 0.00 93.33 0.00 97.01 0.05 95.45 0.00 93.22 0.64 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.653016929
95.68 0.10 98.31 0.08 93.78 0.17 98.43 0.20 93.33 0.00 97.11 0.10 95.45 0.00 93.37 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2804072905
95.77 0.09 98.31 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 94.01 0.64 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1431796259
95.86 0.08 98.31 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 94.60 0.59 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3210442024
95.93 0.07 98.31 0.00 93.78 0.00 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 95.10 0.50 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1408268432
95.99 0.07 98.31 0.00 93.79 0.01 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 95.54 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1582462547
96.06 0.06 98.31 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 95.99 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.4168033624
96.12 0.06 98.31 0.00 93.79 0.00 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 96.44 0.45 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2011702847
96.17 0.05 98.31 0.00 93.81 0.01 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 96.78 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1513408398
96.22 0.05 98.31 0.00 93.81 0.00 98.43 0.00 93.33 0.00 97.11 0.00 95.45 0.00 97.13 0.35 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2696643565
96.26 0.04 98.34 0.03 93.84 0.04 98.62 0.20 93.33 0.00 97.11 0.00 95.45 0.00 97.13 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2697189802
96.30 0.04 98.34 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.11 0.00 95.45 0.00 97.38 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2441952827
96.33 0.04 98.34 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.11 0.00 95.45 0.00 97.62 0.25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2563153241
96.36 0.03 98.34 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.11 0.00 95.45 0.00 97.82 0.20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.167781509
96.38 0.02 98.34 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.11 0.00 95.45 0.00 97.97 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2928672020
96.40 0.02 98.34 0.00 93.84 0.00 98.62 0.00 93.33 0.00 97.11 0.00 95.45 0.00 98.12 0.15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.647912922
96.42 0.02 98.34 0.00 93.87 0.02 98.62 0.00 93.33 0.00 97.13 0.02 95.45 0.00 98.22 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2103676713
96.44 0.02 98.37 0.04 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.03 95.45 0.00 98.27 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3556891962
96.45 0.01 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.37 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.3827254485
96.47 0.01 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.47 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.440899556
96.48 0.01 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.56 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2870232210
96.50 0.01 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.66 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2932751685
96.51 0.01 98.37 0.00 93.87 0.00 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.76 0.10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3709319793
96.52 0.01 98.37 0.00 93.91 0.04 98.62 0.00 93.33 0.00 97.16 0.00 95.45 0.00 98.81 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3836494927
96.53 0.01 98.38 0.01 93.94 0.04 98.62 0.00 93.33 0.00 97.18 0.02 95.45 0.00 98.81 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.3381309831
96.54 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.86 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.1227658707
96.55 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.91 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2020472374
96.55 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 98.96 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3689887782
96.56 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.01 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1447855219
96.57 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.06 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.4274074069
96.57 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.11 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.730098481
96.58 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.16 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.4128020031
96.59 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.21 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2510260483
96.59 0.01 98.38 0.00 93.94 0.00 98.62 0.00 93.33 0.00 97.18 0.00 95.45 0.00 99.26 0.05 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.840428461
96.60 0.01 98.38 0.00 93.97 0.02 98.62 0.00 93.33 0.00 97.19 0.02 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2557573439
96.60 0.01 98.38 0.00 93.99 0.02 98.62 0.00 93.33 0.00 97.19 0.00 95.45 0.00 99.26 0.00 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2665239653

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.601062472
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3446055611
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.555940441
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.87874969
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.971848486
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1084354465
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2449381641
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3474309706
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2652480785
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.626284511
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2186169521
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.36622779
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3922227547
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1042517082
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.100589064
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1003319283
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4037259192
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.916964042
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1229364493
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.1526752439
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.2082471718
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.700982774
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.328024082
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2356241969
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.2218505942
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/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.440295694
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3722871958
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2503350879
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1033962695
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3436040820
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.3946915227
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1066294578
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.366011753
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.4186580539
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3069368978
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/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2343786608
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.613218240
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.3574287343
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.179853498
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.678209768
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2549632649
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.1661821740
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.55063622
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2592398485
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3236702154
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2778054782
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.25643980
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2042562036
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.502895724
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3031705261
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1495284552
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2783537121
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.472162986
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2123482436
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2602237928
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3950787408
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.737603365
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2724765027
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1856954609
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.2922934141
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.4180724216
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.314382315
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2715587210
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1343403118
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2243302508
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2631078427
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.599318965
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1293801616
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/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1744456628
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/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3952096658
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/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.139010457
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.4068304116
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3869577697
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3668983602
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.40384232
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.3854084237
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.491421360
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2505988646
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2939102145
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.429006318
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2892953928
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3906804300
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1213036267
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.1460422701
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3117057739
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1125662035
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.761534855
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.662549111



Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.4081782945 Aug 23 08:47:33 PM UTC 24 Aug 23 08:47:43 PM UTC 24 4606916484 ps
T2 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.130786717 Aug 23 08:46:05 PM UTC 24 Aug 23 08:46:07 PM UTC 24 20420325 ps
T3 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.3646106139 Aug 23 08:46:05 PM UTC 24 Aug 23 08:46:07 PM UTC 24 40259489 ps
T4 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.188802652 Aug 23 08:46:05 PM UTC 24 Aug 23 08:46:07 PM UTC 24 10781803 ps
T5 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.1922062256 Aug 23 08:46:05 PM UTC 24 Aug 23 08:46:07 PM UTC 24 13715298 ps
T6 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.2906599119 Aug 23 08:46:05 PM UTC 24 Aug 23 08:46:09 PM UTC 24 282271070 ps
T7 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.590413316 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:10 PM UTC 24 108485408 ps
T8 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.4075723252 Aug 23 08:46:06 PM UTC 24 Aug 23 08:46:10 PM UTC 24 167888447 ps
T9 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.142237295 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:11 PM UTC 24 118276466 ps
T10 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.1341566798 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:12 PM UTC 24 506279064 ps
T45 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2697189802 Aug 23 08:46:11 PM UTC 24 Aug 23 08:46:13 PM UTC 24 35041543 ps
T11 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.1764743915 Aug 23 08:46:11 PM UTC 24 Aug 23 08:46:13 PM UTC 24 22658259 ps
T12 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.1527587387 Aug 23 08:46:11 PM UTC 24 Aug 23 08:46:13 PM UTC 24 37428609 ps
T13 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.3381309831 Aug 23 08:46:07 PM UTC 24 Aug 23 08:46:14 PM UTC 24 3043579594 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.770224705 Aug 23 08:46:14 PM UTC 24 Aug 23 08:46:16 PM UTC 24 39498748 ps
T14 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.2999915972 Aug 23 08:46:14 PM UTC 24 Aug 23 08:46:16 PM UTC 24 12076748 ps
T15 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2171062112 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:17 PM UTC 24 3779853959 ps
T16 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.2355416688 Aug 23 08:46:07 PM UTC 24 Aug 23 08:46:18 PM UTC 24 3156582453 ps
T38 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1850270157 Aug 23 08:46:16 PM UTC 24 Aug 23 08:46:19 PM UTC 24 116591710 ps
T17 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.1890158568 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:19 PM UTC 24 2114290741 ps
T18 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.440955198 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:19 PM UTC 24 1296033684 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.2804072905 Aug 23 08:46:13 PM UTC 24 Aug 23 08:46:19 PM UTC 24 5702263474 ps
T19 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.4197668659 Aug 23 08:46:08 PM UTC 24 Aug 23 08:46:19 PM UTC 24 2767964466 ps
T111 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.4013818776 Aug 23 08:46:18 PM UTC 24 Aug 23 08:46:21 PM UTC 24 152675202 ps
T20 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.1111555291 Aug 23 08:46:17 PM UTC 24 Aug 23 08:46:23 PM UTC 24 160476155 ps
T46 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.754295352 Aug 23 08:46:20 PM UTC 24 Aug 23 08:46:24 PM UTC 24 185013079 ps
T50 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.919784409 Aug 23 08:46:16 PM UTC 24 Aug 23 08:46:25 PM UTC 24 533704993 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3370380692 Aug 23 08:46:24 PM UTC 24 Aug 23 08:46:26 PM UTC 24 300848587 ps
T95 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.530996988 Aug 23 08:46:25 PM UTC 24 Aug 23 08:46:27 PM UTC 24 44701015 ps
T27 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1401591299 Aug 23 08:46:26 PM UTC 24 Aug 23 08:46:29 PM UTC 24 19388166 ps
T57 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.846475204 Aug 23 08:46:20 PM UTC 24 Aug 23 08:46:31 PM UTC 24 3887779692 ps
T51 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.223503430 Aug 23 08:46:17 PM UTC 24 Aug 23 08:46:31 PM UTC 24 3075135690 ps
T28 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.3709469033 Aug 23 08:46:30 PM UTC 24 Aug 23 08:46:33 PM UTC 24 112007190 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.488835437 Aug 23 08:46:31 PM UTC 24 Aug 23 08:46:34 PM UTC 24 32185511 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.4114558578 Aug 23 08:46:34 PM UTC 24 Aug 23 08:46:37 PM UTC 24 60733660 ps
T52 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.1122316143 Aug 23 08:46:35 PM UTC 24 Aug 23 08:46:39 PM UTC 24 645185161 ps
T29 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.3996437761 Aug 23 08:46:28 PM UTC 24 Aug 23 08:46:40 PM UTC 24 1724405114 ps
T53 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.1348949287 Aug 23 08:46:37 PM UTC 24 Aug 23 08:46:40 PM UTC 24 247280673 ps
T30 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.294714136 Aug 23 08:46:13 PM UTC 24 Aug 23 08:46:44 PM UTC 24 6433866533 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.544799997 Aug 23 08:46:40 PM UTC 24 Aug 23 08:46:44 PM UTC 24 142374580 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2923512548 Aug 23 08:46:31 PM UTC 24 Aug 23 08:46:47 PM UTC 24 3744267897 ps
T47 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.3380671242 Aug 23 08:46:40 PM UTC 24 Aug 23 08:46:47 PM UTC 24 422690300 ps
T31 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.1262170555 Aug 23 08:46:29 PM UTC 24 Aug 23 08:46:49 PM UTC 24 9269383379 ps
T32 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1580038918 Aug 23 08:46:11 PM UTC 24 Aug 23 08:46:53 PM UTC 24 2556902544 ps
T69 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.108790394 Aug 23 08:46:44 PM UTC 24 Aug 23 08:46:53 PM UTC 24 1932537764 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.2380312129 Aug 23 08:46:11 PM UTC 24 Aug 23 08:46:53 PM UTC 24 3479970205 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.4206139591 Aug 23 08:46:54 PM UTC 24 Aug 23 08:46:56 PM UTC 24 11954614 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.2675923790 Aug 23 08:46:54 PM UTC 24 Aug 23 08:46:56 PM UTC 24 17412541 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.897940258 Aug 23 08:46:54 PM UTC 24 Aug 23 08:46:56 PM UTC 24 248236464 ps
T70 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.3556891962 Aug 23 08:46:38 PM UTC 24 Aug 23 08:46:56 PM UTC 24 30191003389 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1956821725 Aug 23 08:46:57 PM UTC 24 Aug 23 08:46:59 PM UTC 24 40459528 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.3990478508 Aug 23 08:46:57 PM UTC 24 Aug 23 08:46:59 PM UTC 24 27320429 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3950418330 Aug 23 08:46:56 PM UTC 24 Aug 23 08:47:00 PM UTC 24 1220314521 ps
T68 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.2885152503 Aug 23 08:46:58 PM UTC 24 Aug 23 08:47:00 PM UTC 24 20462487 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.351156796 Aug 23 08:47:00 PM UTC 24 Aug 23 08:47:02 PM UTC 24 78601996 ps
T379 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.4228447315 Aug 23 08:47:01 PM UTC 24 Aug 23 08:47:04 PM UTC 24 30396557 ps
T93 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.1258492121 Aug 23 08:47:05 PM UTC 24 Aug 23 08:47:08 PM UTC 24 59603899 ps
T41 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.520385205 Aug 23 08:46:22 PM UTC 24 Aug 23 08:47:10 PM UTC 24 23868906078 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.1877708246 Aug 23 08:46:50 PM UTC 24 Aug 23 08:47:11 PM UTC 24 4008218690 ps
T119 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.1406652451 Aug 23 08:47:01 PM UTC 24 Aug 23 08:47:12 PM UTC 24 15026941971 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.3438469574 Aug 23 08:47:05 PM UTC 24 Aug 23 08:47:12 PM UTC 24 4793044865 ps
T120 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.1409388893 Aug 23 08:47:03 PM UTC 24 Aug 23 08:47:18 PM UTC 24 12077563504 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.990954378 Aug 23 08:47:18 PM UTC 24 Aug 23 08:47:21 PM UTC 24 391968210 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.3063211157 Aug 23 08:47:11 PM UTC 24 Aug 23 08:47:22 PM UTC 24 1326947405 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.4105400701 Aug 23 08:47:21 PM UTC 24 Aug 23 08:47:23 PM UTC 24 28667982 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.1151957438 Aug 23 08:46:45 PM UTC 24 Aug 23 08:47:24 PM UTC 24 1751139963 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.415393464 Aug 23 08:47:25 PM UTC 24 Aug 23 08:47:46 PM UTC 24 6480323868 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.1747181578 Aug 23 08:47:24 PM UTC 24 Aug 23 08:47:25 PM UTC 24 58173973 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3666596590 Aug 23 08:46:09 PM UTC 24 Aug 23 08:47:26 PM UTC 24 54374607621 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3875902046 Aug 23 08:47:26 PM UTC 24 Aug 23 08:47:28 PM UTC 24 86613828 ps
T60 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.988262564 Aug 23 08:47:00 PM UTC 24 Aug 23 08:47:28 PM UTC 24 9186139833 ps
T94 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1667608696 Aug 23 08:46:48 PM UTC 24 Aug 23 08:47:29 PM UTC 24 3837064141 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.1256168588 Aug 23 08:47:24 PM UTC 24 Aug 23 08:47:31 PM UTC 24 2177729958 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2006100725 Aug 23 08:47:28 PM UTC 24 Aug 23 08:47:32 PM UTC 24 487709381 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.2377623504 Aug 23 08:46:20 PM UTC 24 Aug 23 08:47:32 PM UTC 24 5743129742 ps
T371 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.724344368 Aug 23 08:47:26 PM UTC 24 Aug 23 08:47:33 PM UTC 24 764332497 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.762095787 Aug 23 08:47:30 PM UTC 24 Aug 23 08:47:33 PM UTC 24 42286365 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.3157293405 Aug 23 08:47:32 PM UTC 24 Aug 23 08:47:35 PM UTC 24 107232172 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3236599100 Aug 23 08:47:33 PM UTC 24 Aug 23 08:47:38 PM UTC 24 475169632 ps
T372 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.3100616229 Aug 23 08:49:03 PM UTC 24 Aug 23 08:49:34 PM UTC 24 8224642081 ps
T56 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.2714607934 Aug 23 08:47:27 PM UTC 24 Aug 23 08:47:40 PM UTC 24 2320898375 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2790920156 Aug 23 08:47:45 PM UTC 24 Aug 23 08:47:47 PM UTC 24 88006556 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.173763270 Aug 23 08:47:47 PM UTC 24 Aug 23 08:47:48 PM UTC 24 15203249 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.315240327 Aug 23 08:47:48 PM UTC 24 Aug 23 08:47:49 PM UTC 24 114417584 ps
T238 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.1096852084 Aug 23 08:47:29 PM UTC 24 Aug 23 08:47:50 PM UTC 24 1768272167 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.1033962695 Aug 23 08:47:51 PM UTC 24 Aug 23 08:47:53 PM UTC 24 134827529 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.2503350879 Aug 23 08:47:51 PM UTC 24 Aug 23 08:47:54 PM UTC 24 37496272 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.3722871958 Aug 23 08:47:50 PM UTC 24 Aug 23 08:47:56 PM UTC 24 923398853 ps
T58 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.653016929 Aug 23 08:46:48 PM UTC 24 Aug 23 08:47:58 PM UTC 24 5443023301 ps
T87 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2932751685 Aug 23 08:47:12 PM UTC 24 Aug 23 08:48:01 PM UTC 24 19919983855 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2793019747 Aug 23 08:47:54 PM UTC 24 Aug 23 08:48:03 PM UTC 24 8832655891 ps
T272 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.1865189896 Aug 23 08:48:00 PM UTC 24 Aug 23 08:48:04 PM UTC 24 462069315 ps
T118 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.909047572 Aug 23 08:47:30 PM UTC 24 Aug 23 08:48:05 PM UTC 24 5763994444 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2534453038 Aug 23 08:48:02 PM UTC 24 Aug 23 08:48:06 PM UTC 24 535481550 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.3542386801 Aug 23 08:47:54 PM UTC 24 Aug 23 08:48:07 PM UTC 24 2113009537 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.63588357 Aug 23 08:48:05 PM UTC 24 Aug 23 08:48:09 PM UTC 24 54685469 ps
T48 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1152486608 Aug 23 08:46:09 PM UTC 24 Aug 23 08:48:09 PM UTC 24 10297010453 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.1108835422 Aug 23 08:47:57 PM UTC 24 Aug 23 08:48:12 PM UTC 24 7413685820 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.805672800 Aug 23 08:47:34 PM UTC 24 Aug 23 08:48:12 PM UTC 24 9323365937 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.740156705 Aug 23 08:48:07 PM UTC 24 Aug 23 08:48:12 PM UTC 24 1536870605 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.805715015 Aug 23 08:48:11 PM UTC 24 Aug 23 08:48:13 PM UTC 24 102480906 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.3436040820 Aug 23 08:48:00 PM UTC 24 Aug 23 08:48:13 PM UTC 24 9541221084 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.14219604 Aug 23 08:47:40 PM UTC 24 Aug 23 08:48:14 PM UTC 24 9055364997 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.1816332033 Aug 23 08:48:14 PM UTC 24 Aug 23 08:48:16 PM UTC 24 123045151 ps
T276 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.2243302508 Aug 23 08:49:09 PM UTC 24 Aug 23 08:49:42 PM UTC 24 4091458346 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.366011753 Aug 23 08:48:14 PM UTC 24 Aug 23 08:48:16 PM UTC 24 72546201 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2155166673 Aug 23 08:48:14 PM UTC 24 Aug 23 08:48:18 PM UTC 24 450006905 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.613218240 Aug 23 08:48:16 PM UTC 24 Aug 23 08:48:18 PM UTC 24 308438084 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2343786608 Aug 23 08:48:17 PM UTC 24 Aug 23 08:48:19 PM UTC 24 31924785 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.4202510782 Aug 23 08:48:11 PM UTC 24 Aug 23 08:48:21 PM UTC 24 5900512637 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.440295694 Aug 23 08:47:50 PM UTC 24 Aug 23 08:48:21 PM UTC 24 5247637006 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.3576934299 Aug 23 08:48:17 PM UTC 24 Aug 23 08:48:24 PM UTC 24 1184507415 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.982425503 Aug 23 08:48:14 PM UTC 24 Aug 23 08:48:24 PM UTC 24 1700598840 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.1066294578 Aug 23 08:48:20 PM UTC 24 Aug 23 08:48:25 PM UTC 24 1470378000 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1777724582 Aug 23 08:48:17 PM UTC 24 Aug 23 08:48:26 PM UTC 24 1072324990 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.851308121 Aug 23 08:48:25 PM UTC 24 Aug 23 08:48:30 PM UTC 24 180589499 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.3574287343 Aug 23 08:48:19 PM UTC 24 Aug 23 08:48:30 PM UTC 24 3549492149 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.4120385388 Aug 23 08:47:09 PM UTC 24 Aug 23 08:48:30 PM UTC 24 12947939002 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.3946915227 Aug 23 08:48:31 PM UTC 24 Aug 23 08:48:33 PM UTC 24 13230223 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.2549632649 Aug 23 08:48:31 PM UTC 24 Aug 23 08:48:33 PM UTC 24 20997911 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.3236464143 Aug 23 08:48:22 PM UTC 24 Aug 23 08:48:33 PM UTC 24 3124964932 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.72122544 Aug 23 08:48:17 PM UTC 24 Aug 23 08:48:33 PM UTC 24 1409552472 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.4068304116 Aug 23 08:49:37 PM UTC 24 Aug 23 08:49:39 PM UTC 24 43561835 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.2602237928 Aug 23 08:48:34 PM UTC 24 Aug 23 08:48:36 PM UTC 24 292227395 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.2783537121 Aug 23 08:48:34 PM UTC 24 Aug 23 08:48:39 PM UTC 24 1053887202 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2123482436 Aug 23 08:48:37 PM UTC 24 Aug 23 08:48:40 PM UTC 24 113003160 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.2281374332 Aug 23 08:47:12 PM UTC 24 Aug 23 08:48:42 PM UTC 24 12629061051 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.472162986 Aug 23 08:48:34 PM UTC 24 Aug 23 08:48:45 PM UTC 24 2924077418 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.502895724 Aug 23 08:48:37 PM UTC 24 Aug 23 08:48:45 PM UTC 24 449743928 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2042562036 Aug 23 08:48:39 PM UTC 24 Aug 23 08:48:48 PM UTC 24 10064322381 ps
T112 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1910624873 Aug 23 08:47:13 PM UTC 24 Aug 23 08:48:53 PM UTC 24 21328973000 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.678209768 Aug 23 08:48:45 PM UTC 24 Aug 23 08:48:53 PM UTC 24 3569728748 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.25643980 Aug 23 08:48:42 PM UTC 24 Aug 23 08:48:53 PM UTC 24 460292531 ps
T297 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.3950787408 Aug 23 08:48:45 PM UTC 24 Aug 23 08:48:53 PM UTC 24 1347000557 ps
T234 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.2778054782 Aug 23 08:48:41 PM UTC 24 Aug 23 08:48:54 PM UTC 24 4587502775 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.1661821740 Aug 23 08:48:54 PM UTC 24 Aug 23 08:48:56 PM UTC 24 13404754 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.3031705261 Aug 23 08:48:53 PM UTC 24 Aug 23 08:48:58 PM UTC 24 81133263 ps
T37 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.1495284552 Aug 23 08:48:57 PM UTC 24 Aug 23 08:48:59 PM UTC 24 53854929 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.179853498 Aug 23 08:48:59 PM UTC 24 Aug 23 08:49:00 PM UTC 24 46605454 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.1856954609 Aug 23 08:49:00 PM UTC 24 Aug 23 08:49:02 PM UTC 24 31146425 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2592398485 Aug 23 08:48:49 PM UTC 24 Aug 23 08:49:02 PM UTC 24 558374398 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2466029331 Aug 23 08:48:31 PM UTC 24 Aug 23 08:49:05 PM UTC 24 4568295499 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3249925052 Aug 23 08:49:03 PM UTC 24 Aug 23 08:49:05 PM UTC 24 145093179 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.3069368978 Aug 23 08:48:27 PM UTC 24 Aug 23 08:49:07 PM UTC 24 17193016517 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1744456628 Aug 23 08:49:02 PM UTC 24 Aug 23 08:49:07 PM UTC 24 773942999 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.3780734861 Aug 23 08:49:06 PM UTC 24 Aug 23 08:49:08 PM UTC 24 123774787 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.2631078427 Aug 23 08:49:08 PM UTC 24 Aug 23 08:49:11 PM UTC 24 934191444 ps
T248 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.1343403118 Aug 23 08:49:08 PM UTC 24 Aug 23 08:49:15 PM UTC 24 865897564 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.55063622 Aug 23 08:48:55 PM UTC 24 Aug 23 08:49:18 PM UTC 24 6190195621 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.2724765027 Aug 23 08:49:16 PM UTC 24 Aug 23 08:49:22 PM UTC 24 1864169106 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.314382315 Aug 23 08:49:18 PM UTC 24 Aug 23 08:49:23 PM UTC 24 251109308 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.3952096658 Aug 23 08:49:12 PM UTC 24 Aug 23 08:49:23 PM UTC 24 7421991288 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.957519247 Aug 23 08:48:07 PM UTC 24 Aug 23 08:49:27 PM UTC 24 11007636193 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.599318965 Aug 23 08:49:06 PM UTC 24 Aug 23 08:49:32 PM UTC 24 9424212048 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.1293801616 Aug 23 08:49:23 PM UTC 24 Aug 23 08:49:33 PM UTC 24 3087278922 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.737603365 Aug 23 08:49:35 PM UTC 24 Aug 23 08:49:37 PM UTC 24 48692927 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.2809922324 Aug 23 08:48:18 PM UTC 24 Aug 23 08:49:47 PM UTC 24 39837349454 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.3117057739 Aug 23 08:49:41 PM UTC 24 Aug 23 08:49:48 PM UTC 24 916725119 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.761534855 Aug 23 08:49:47 PM UTC 24 Aug 23 08:49:49 PM UTC 24 23934552 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1125662035 Aug 23 08:49:48 PM UTC 24 Aug 23 08:49:50 PM UTC 24 187899559 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.1460422701 Aug 23 08:49:43 PM UTC 24 Aug 23 08:49:54 PM UTC 24 25671061975 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.429006318 Aug 23 08:49:51 PM UTC 24 Aug 23 08:49:54 PM UTC 24 119680749 ps
T63 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2715587210 Aug 23 08:49:23 PM UTC 24 Aug 23 08:49:59 PM UTC 24 8473367957 ps
T64 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.3610434588 Aug 23 08:47:36 PM UTC 24 Aug 23 08:50:00 PM UTC 24 21048481457 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.662549111 Aug 23 08:49:59 PM UTC 24 Aug 23 08:50:03 PM UTC 24 535568313 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.139010457 Aug 23 08:50:01 PM UTC 24 Aug 23 08:50:04 PM UTC 24 111442459 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.2892953928 Aug 23 08:49:49 PM UTC 24 Aug 23 08:50:08 PM UTC 24 31407063001 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.2939102145 Aug 23 08:49:55 PM UTC 24 Aug 23 08:50:09 PM UTC 24 1112376101 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.2073698022 Aug 23 08:47:38 PM UTC 24 Aug 23 08:50:10 PM UTC 24 387491519983 ps
T49 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.3236702154 Aug 23 08:48:53 PM UTC 24 Aug 23 08:50:11 PM UTC 24 8783857479 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.3854084237 Aug 23 08:50:03 PM UTC 24 Aug 23 08:50:15 PM UTC 24 1741682439 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3906804300 Aug 23 08:50:10 PM UTC 24 Aug 23 08:50:16 PM UTC 24 2622387584 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.666875822 Aug 23 08:48:56 PM UTC 24 Aug 23 08:50:18 PM UTC 24 5921020128 ps
T61 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.1582462547 Aug 23 08:46:20 PM UTC 24 Aug 23 08:50:18 PM UTC 24 174812376787 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3924848717 Aug 23 08:50:17 PM UTC 24 Aug 23 08:50:19 PM UTC 24 64335035 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.2505988646 Aug 23 08:49:55 PM UTC 24 Aug 23 08:50:20 PM UTC 24 10642370241 ps
T65 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1685058542 Aug 23 08:47:17 PM UTC 24 Aug 23 08:50:20 PM UTC 24 24999285327 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.1926866220 Aug 23 08:51:13 PM UTC 24 Aug 23 08:52:02 PM UTC 24 23156513542 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.925353543 Aug 23 08:50:19 PM UTC 24 Aug 23 08:50:21 PM UTC 24 38631711 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.2466621205 Aug 23 08:50:21 PM UTC 24 Aug 23 08:50:23 PM UTC 24 34666485 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.703892453 Aug 23 08:50:21 PM UTC 24 Aug 23 08:50:23 PM UTC 24 112067570 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.2696643565 Aug 23 08:46:20 PM UTC 24 Aug 23 08:50:25 PM UTC 24 37276446999 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.4258168313 Aug 23 08:50:19 PM UTC 24 Aug 23 08:50:27 PM UTC 24 8162180314 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.1188636917 Aug 23 08:49:34 PM UTC 24 Aug 23 08:50:28 PM UTC 24 11589938963 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.3245999417 Aug 23 08:48:27 PM UTC 24 Aug 23 08:50:32 PM UTC 24 43006253232 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.3985842513 Aug 23 08:50:28 PM UTC 24 Aug 23 08:50:32 PM UTC 24 91684786 ps
T66 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2838463975 Aug 23 08:50:23 PM UTC 24 Aug 23 08:50:32 PM UTC 24 257006312 ps
T62 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.2020472374 Aug 23 08:46:21 PM UTC 24 Aug 23 08:50:32 PM UTC 24 184627359828 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2816139699 Aug 23 08:50:25 PM UTC 24 Aug 23 08:50:33 PM UTC 24 721691631 ps
T253 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.3233943668 Aug 23 08:50:24 PM UTC 24 Aug 23 08:50:33 PM UTC 24 772550711 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.269698550 Aug 23 08:46:41 PM UTC 24 Aug 23 08:50:34 PM UTC 24 35682589930 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.3431976914 Aug 23 08:50:21 PM UTC 24 Aug 23 08:50:36 PM UTC 24 54619013824 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.2903680685 Aug 23 08:50:21 PM UTC 24 Aug 23 08:50:36 PM UTC 24 1648726674 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2599647207 Aug 23 08:50:37 PM UTC 24 Aug 23 08:50:39 PM UTC 24 62704897 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.1194751431 Aug 23 08:50:37 PM UTC 24 Aug 23 08:50:39 PM UTC 24 23352824 ps
T370 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.40384232 Aug 23 08:50:12 PM UTC 24 Aug 23 08:50:40 PM UTC 24 9566443754 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3687303643 Aug 23 08:50:27 PM UTC 24 Aug 23 08:50:40 PM UTC 24 14462288465 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.72595267 Aug 23 08:50:34 PM UTC 24 Aug 23 08:50:42 PM UTC 24 2380290447 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.2590496339 Aug 23 08:50:41 PM UTC 24 Aug 23 08:50:43 PM UTC 24 78293095 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.2017049127 Aug 23 08:50:41 PM UTC 24 Aug 23 08:50:44 PM UTC 24 51988197 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.2612773245 Aug 23 08:50:32 PM UTC 24 Aug 23 08:50:49 PM UTC 24 6716117880 ps
T67 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3184950035 Aug 23 08:50:44 PM UTC 24 Aug 23 08:50:49 PM UTC 24 861154235 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2751171482 Aug 23 08:50:42 PM UTC 24 Aug 23 08:50:50 PM UTC 24 881227396 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.806404247 Aug 23 08:50:50 PM UTC 24 Aug 23 08:50:53 PM UTC 24 295981052 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.966963628 Aug 23 08:47:33 PM UTC 24 Aug 23 08:50:53 PM UTC 24 30593139238 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3516606252 Aug 23 08:50:51 PM UTC 24 Aug 23 08:50:54 PM UTC 24 31710900 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.4099103851 Aug 23 08:50:40 PM UTC 24 Aug 23 08:50:55 PM UTC 24 9082101253 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.663579511 Aug 23 08:50:50 PM UTC 24 Aug 23 08:50:55 PM UTC 24 369922117 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.1954469369 Aug 23 08:50:41 PM UTC 24 Aug 23 08:50:59 PM UTC 24 13897197301 ps
T295 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1541018756 Aug 23 08:50:45 PM UTC 24 Aug 23 08:50:59 PM UTC 24 1557172015 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.1400655030 Aug 23 08:50:55 PM UTC 24 Aug 23 08:51:00 PM UTC 24 396305710 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1764835190 Aug 23 08:50:59 PM UTC 24 Aug 23 08:51:01 PM UTC 24 50799720 ps
T229 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.4180724216 Aug 23 08:49:33 PM UTC 24 Aug 23 08:51:02 PM UTC 24 33091214131 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.1154089382 Aug 23 08:50:32 PM UTC 24 Aug 23 08:51:02 PM UTC 24 1943634745 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2202705279 Aug 23 08:51:00 PM UTC 24 Aug 23 08:51:02 PM UTC 24 10914977 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.863420590 Aug 23 08:51:55 PM UTC 24 Aug 23 08:51:57 PM UTC 24 58488983 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1518829754 Aug 23 08:51:03 PM UTC 24 Aug 23 08:51:04 PM UTC 24 103867942 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1178563874 Aug 23 08:51:05 PM UTC 24 Aug 23 08:51:07 PM UTC 24 180304344 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.398877174 Aug 23 08:51:05 PM UTC 24 Aug 23 08:51:07 PM UTC 24 18428713 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.3406693873 Aug 23 08:51:03 PM UTC 24 Aug 23 08:51:08 PM UTC 24 2357678669 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2573414031 Aug 23 08:51:08 PM UTC 24 Aug 23 08:51:12 PM UTC 24 937775349 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.2658005013 Aug 23 08:51:03 PM UTC 24 Aug 23 08:51:14 PM UTC 24 3089802213 ps
T269 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.4075422458 Aug 23 08:51:09 PM UTC 24 Aug 23 08:51:19 PM UTC 24 2659134657 ps
T256 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.876696775 Aug 23 08:51:07 PM UTC 24 Aug 23 08:51:20 PM UTC 24 1677835964 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.4274074069 Aug 23 08:51:15 PM UTC 24 Aug 23 08:51:27 PM UTC 24 2972003060 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.491421360 Aug 23 08:50:05 PM UTC 24 Aug 23 08:51:28 PM UTC 24 43124495543 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1447855219 Aug 23 08:51:21 PM UTC 24 Aug 23 08:51:32 PM UTC 24 3100367831 ps
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T437 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2835225917 Aug 23 08:51:52 PM UTC 24 Aug 23 08:51:54 PM UTC 24 129520581 ps
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T71 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3146017565 Aug 23 08:50:34 PM UTC 24 Aug 23 08:51:56 PM UTC 24 5992373874 ps
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T83 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.482377960 Aug 23 08:52:02 PM UTC 24 Aug 23 08:52:07 PM UTC 24 510386053 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.3158062526 Aug 23 08:52:03 PM UTC 24 Aug 23 08:52:10 PM UTC 24 1209798874 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.2136587963 Aug 23 08:52:04 PM UTC 24 Aug 23 08:52:12 PM UTC 24 651564171 ps
T86 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.1399213116 Aug 23 08:52:11 PM UTC 24 Aug 23 08:52:17 PM UTC 24 1661014874 ps
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T439 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.2824726679 Aug 23 08:52:00 PM UTC 24 Aug 23 08:52:21 PM UTC 24 17448506755 ps
T275 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1716315775 Aug 23 08:51:29 PM UTC 24 Aug 23 08:52:23 PM UTC 24 29038621448 ps
T270 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.2735296032 Aug 23 08:50:34 PM UTC 24 Aug 23 08:52:26 PM UTC 24 93887720788 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3869577697 Aug 23 08:50:10 PM UTC 24 Aug 23 08:52:31 PM UTC 24 18126091800 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.3536897815 Aug 23 08:52:19 PM UTC 24 Aug 23 08:52:32 PM UTC 24 3954680388 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.3689887782 Aug 23 08:50:35 PM UTC 24 Aug 23 08:52:33 PM UTC 24 49226266372 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.440899556 Aug 23 08:50:32 PM UTC 24 Aug 23 08:52:33 PM UTC 24 15366037736 ps
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