Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	34713	1			T13	2		T15	6		T16	8
auto[SpiFlashAddrCfg]	7738	1			T13	4		T20	4		T52	2
auto[SpiFlashAddr3b]	9570	1			T1	1		T10	1		T13	2
auto[SpiFlashAddr4b]	7841	1			T10	2		T13	6		T16	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34728

1

T1

1

T10

3

T15

6

auto[1]

25134

1

T13

14

T50

12

T32

54

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31877

1

T10

1

T13

4

T15

6

auto[1]

27985

1

T1

1

T10

2

T13

10

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39562	1			T13	4		T15	6		T16	2
values[1]	1101	1			T32	2		T22	4		T41	8
values[2]	1488	1			T10	1		T17	2		T20	4
values[3]	1451	1			T53	2		T47	2		T22	10
values[4]	1505	1			T1	1		T10	1		T13	2
values[5]	1466	1			T16	6		T17	2		T32	1
values[6]	1533	1			T54	4		T47	5		T32	2
values[7]	1464	1			T51	4		T52	2		T32	2
values[8]	10292	1			T10	1		T13	8		T16	8

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26534

1

T13

14

T15

6

T16

16

auto[1]

33328

1

T1

1

T10

3

T47

7

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56399

1

T1

1

T10

3

T13

14

write

3463

1

T50

2

T54

6

T32

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19798

1

T1

1

T10

3

T13

4

valids[0x1]

40064

1

T13

10

T16

14

T17

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1637	1			T19	4		T52	2		T32	2
internal_process_ops[0x5a]	1636	1			T32	2		T22	6		T41	9
internal_process_ops[0x05]	20131	1			T17	2		T19	2		T52	4
internal_process_ops[0x35]	1644	1			T13	2		T50	4		T51	2
internal_process_ops[0x15]	1729	1			T16	2		T19	6		T32	2
internal_process_ops[0x03]	1036	1			T13	2		T17	2		T51	2
internal_process_ops[0x0b]	1062	1			T13	2		T20	4		T51	4
internal_process_ops[0x3b]	1052	1			T10	1		T20	8		T53	6
internal_process_ops[0x6b]	1054	1			T10	1		T17	2		T32	1
internal_process_ops[0xbb]	985	1			T1	1		T50	2		T51	2
internal_process_ops[0xeb]	991	1			T10	1		T20	2		T52	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58132

1

T1

1

T10

3

T13

14

auto[1]

1730

1

T50

2

T32

9

T22

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57418

1

T1

1

T10

3

T13

14

auto[1]

2444

1

T32

7

T41

2

T42

9

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9102

1

T15

6

T16

8

T17

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5037

1

T13

2

T50

4

T60

4

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1806

1

T20

4

T52

2

T53

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1532

1

T13

4

T60

2

T94

1

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2235

1

T16

2

T17

6

T51

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1980

1

T13

2

T60

6

T94

1

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1806

1

T16

6

T17

2

T20

10

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1581

1

T13

6

T50

6

T60

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

105

1

T58

3

T188

2

T48

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

98

1

T58

3

T48

2

T63

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

80

1

T58

2

T48

1

T63

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T48

1

T36

3

T49

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

131

1

T54

6

T48

4

T189

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

61

1

T65

1

T62

1

T190

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

71

1

T48

1

T64

1

T71

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

114

1

T55

2

T48

4

T61

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

83

1

T191

2

T192

4

T193

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

85

1

T63

1

T190

1

T71

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

71

1

T71

2

T194

3

T195

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

83

1

T48

1

T63

1

T61

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

106

1

T56

2

T189

6

T191

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

84

1

T48

2

T64

5

T61

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

72

1

T58

3

T48

1

T49

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

106

1

T50

2

T49

3

T61

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12051

1

T32

16

T22

25

T41

132

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7636

1

T32

36

T22

19

T41

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1787

1

T47

5

T32

4

T22

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1776

1

T32

4

T22

17

T41

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2385

1

T1

1

T10

1

T47

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2131

1

T32

4

T22

17

T41

27

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1786

1

T10

2

T47

1

T32

1

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1768

1

T32

5

T22

14

T41

17

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

137

1

T32

2

T42

4

T44

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

113

1

T44

1

T87

1

T196

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

131

1

T22

1

T42

2

T103

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

118

1

T41

3

T88

1

T197

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

121

1

T44

4

T103

1

T197

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

114

1

T22

2

T41

1

T42

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

124

1

T42

1

T44

1

T103

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

101

1

T41

2

T42

1

T103

7

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

109

1

T88

1

T103

6

T112

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

144

1

T32

6

T22

1

T44

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

143

1

T32

1

T44

2

T88

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

121

1

T88

1

T103

2

T198

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

130

1

T42

3

T44

1

T103

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

149

1

T22

3

T41

3

T42

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

119

1

T32

1

T44

1

T87

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

134

1

T32

3

T41

2

T42

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3298	1			T15	6		T17	2		T57	6
auto[0]	values[0]	valids[0x1]	13385	1			T13	4		T16	2		T17	2
auto[0]	values[1]	valids[0x1]	489	1			T94	1		T58	2		T118	4
auto[0]	values[2]	valids[0x0]	452	1			T54	2		T48	2		T199	2
auto[0]	values[2]	valids[0x1]	282	1			T17	2		T20	4		T94	2
auto[0]	values[3]	valids[0x0]	500	1			T70	2		T55	2		T56	4
auto[0]	values[3]	valids[0x1]	199	1			T53	2		T48	5		T200	2
auto[0]	values[4]	valids[0x0]	485	1			T20	8		T70	4		T58	6
auto[0]	values[4]	valids[0x1]	265	1			T13	2		T60	2		T94	1
auto[0]	values[5]	valids[0x0]	443	1			T58	1		T36	6		T64	9
auto[0]	values[5]	valids[0x1]	242	1			T16	6		T17	2		T58	3
auto[0]	values[6]	valids[0x0]	482	1			T54	4		T92	2		T119	2
auto[0]	values[6]	valids[0x1]	276	1			T120	2		T201	10		T48	4
auto[0]	values[7]	valids[0x0]	461	1			T52	2		T56	2		T58	7
auto[0]	values[7]	valids[0x1]	274	1			T51	4		T58	3		T48	3
auto[0]	values[8]	valids[0x0]	3066	1			T13	4		T16	2		T17	2
auto[0]	values[8]	valids[0x1]	1935	1			T13	4		T16	6		T50	2
auto[1]	values[0]	valids[0x0]	4699	1			T32	13		T22	19		T41	47
auto[1]	values[0]	valids[0x1]	18180	1			T32	59		T22	39		T41	120
auto[1]	values[1]	valids[0x1]	612	1			T32	2		T22	4		T41	8
auto[1]	values[2]	valids[0x0]	457	1			T10	1		T41	2		T42	3
auto[1]	values[2]	valids[0x1]	297	1			T32	1		T22	4		T41	5
auto[1]	values[3]	valids[0x0]	468	1			T47	2		T22	9		T41	4
auto[1]	values[3]	valids[0x1]	284	1			T22	1		T41	6		T42	4
auto[1]	values[4]	valids[0x0]	454	1			T1	1		T10	1		T32	1
auto[1]	values[4]	valids[0x1]	301	1			T32	1		T22	2		T41	1
auto[1]	values[5]	valids[0x0]	472	1			T32	1		T22	3		T41	2
auto[1]	values[5]	valids[0x1]	309	1			T22	3		T41	3		T44	6
auto[1]	values[6]	valids[0x0]	470	1			T47	2		T32	1		T22	10
auto[1]	values[6]	valids[0x1]	305	1			T47	3		T32	1		T22	3
auto[1]	values[7]	valids[0x0]	428	1			T32	1		T22	4		T41	4
auto[1]	values[7]	valids[0x1]	301	1			T32	1		T41	2		T42	2
auto[1]	values[8]	valids[0x0]	3163	1			T10	1		T32	5		T22	19
auto[1]	values[8]	valids[0x1]	2128	1			T32	4		T22	14		T41	32