Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3438862

1

T1

907

T7

1

T9

9

auto[1]

29206

1

T32

31

T41

70

T42

198

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974341

1

T1

907

T7

1

T9

9

auto[1]

2493727

1

T17

4614

T19

5618

T51

256

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	585036	1			T7	1		T9	7		T10	75
auto[524288:1048575]	393191	1			T1	905		T19	951		T57	676
auto[1048576:1572863]	387874	1			T1	2		T15	13		T19	121
auto[1572864:2097151]	413248	1			T19	62		T57	1		T51	526
auto[2097152:2621439]	442403	1			T15	6		T19	299		T20	103
auto[2621440:3145727]	405539	1			T9	2		T15	52		T19	1417
auto[3145728:3670015]	455219	1			T10	52		T15	915		T19	253
auto[3670016:4194303]	385558	1			T15	1013		T19	248		T20	167

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2530770

1

T1

21

T7

1

T9

7

auto[1]

937298

1

T1

886

T9

2

T10

121

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2975578

1

T1

907

T7

1

T9

9

auto[1]

492490

1

T15

63

T32

128

T22

512

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	186411	1			T7	1		T9	7		T10	75
auto[0]	auto[0]	auto[0:524287]	auto[1]	343898	1			T17	4614		T19	5293		T52	223
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	104929	1			T1	905		T19	947		T57	676
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	230723	1			T19	4		T32	1		T22	84
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	103384	1			T1	2		T15	6		T19	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	211178	1			T19	119		T52	225		T22	1408
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	117734	1			T19	58		T57	1		T51	397
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	230147	1			T19	4		T51	129		T22	1418
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	122561	1			T15	2		T19	149		T20	103
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	248197	1			T19	150		T32	1		T22	1122
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	131563	1			T9	2		T19	1397		T20	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	213951	1			T19	20		T51	127		T41	128
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	97007	1			T10	52		T15	915		T19	225
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	264835	1			T19	28		T32	4		T22	256
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	94449	1			T15	1013		T19	248		T20	167
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	250188	1			T32	769		T22	128		T41	2644
auto[0]	auto[1]	auto[0:524287]	auto[0]	1308	1			T41	5		T42	3		T44	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	48050	1			T41	428		T42	2231		T44	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2765	1			T41	1		T44	1		T87	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	51906	1			T44	1		T87	218		T65	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	1180	1			T15	7		T44	1		T87	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	68687	1			T22	512		T87	1179		T48	2370
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	3008	1			T41	2		T44	2		T58	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	58376	1			T44	258		T58	6		T48	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1447	1			T15	4		T44	1		T214	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	66731	1			T32	128		T44	128		T58	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	727	1			T15	52		T41	4		T44	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	55843	1			T41	1		T94	515		T88	388
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	779	1			T42	4		T44	2		T58	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	89175	1			T41	128		T42	4240		T48	5433
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	816	1			T42	3		T214	6		T58	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	36909	1			T42	2		T58	1		T103	42
auto[1]	auto[0]	auto[0:524287]	auto[0]	611	1			T48	1		T36	3		T89	2
auto[1]	auto[0]	auto[0:524287]	auto[1]	3930	1			T48	10		T36	13		T89	10
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	393	1			T32	1		T44	1		T48	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2155	1			T32	1		T44	9		T48	53
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	406	1			T42	1		T44	1		T58	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2532	1			T42	25		T44	7		T58	25
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	433	1			T42	1		T44	1		T48	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	3163	1			T42	14		T44	43		T48	14
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	365	1			T32	1		T48	1		T103	17
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	2361	1			T32	2		T48	53		T103	172
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	413	1			T42	2		T88	1		T103	12
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2501	1			T42	74		T88	3		T64	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	327	1			T32	4		T41	1		T44	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2442	1			T32	13		T41	63		T44	103
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	423	1			T32	1		T42	1		T58	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1968	1			T32	8		T58	38		T87	27
auto[1]	auto[1]	auto[0:524287]	auto[0]	142	1			T42	2		T44	1		T48	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	686	1			T42	36		T44	12		T48	16
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	88	1			T44	1		T63	3		T65	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	232	1			T44	4		T65	9		T282	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	112	1			T87	2		T48	1		T88	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	395	1			T87	16		T48	19		T88	11
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	76	1			T44	2		T58	1		T212	7
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	311	1			T44	27		T58	41		T236	7
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	138	1			T226	3		T121	6		T213	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	603	1			T226	32		T265	15		T283	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	81	1			T41	1		T112	1		T197	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	460	1			T41	5		T225	7		T190	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	138	1			T103	3		T63	3		T64	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	516	1			T64	2		T197	3		T65	6
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	127	1			T42	2		T58	1		T103	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	678	1			T42	40		T103	86		T112	5

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2020888	1			T1	21		T7	1		T9	7
auto[0]	auto[0]	auto[1]	930267	1			T1	886		T9	2		T10	121
auto[0]	auto[1]	auto[0]	481385	1			T15	5		T32	128		T22	512
auto[0]	auto[1]	auto[1]	6322	1			T15	58		T41	1		T42	2
auto[1]	auto[0]	auto[0]	23847	1			T32	31		T41	64		T42	117
auto[1]	auto[0]	auto[1]	576	1			T42	1		T44	1		T58	1
auto[1]	auto[1]	auto[0]	4650	1			T41	6		T42	80		T44	47
auto[1]	auto[1]	auto[1]	133	1			T87	1		T48	2		T103	4