Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2542175	1			T1	1		T2	1		T3	1
all_pins[1]	2542175	1			T1	1		T2	1		T3	1
all_pins[2]	2542175	1			T1	1		T2	1		T3	1
all_pins[3]	2542175	1			T1	1		T2	1		T3	1
all_pins[4]	2542175	1			T1	1		T2	1		T3	1
all_pins[5]	2542175	1			T1	1		T2	1		T3	1
all_pins[6]	2542175	1			T1	1		T2	1		T3	1
all_pins[7]	2542175	1			T1	1		T2	1		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	20323465	1			T1	8		T2	8		T3	8
values[0x1]	13935	1			T41	21		T24	15		T35	45
transitions[0x0=>0x1]	12486	1			T41	17		T24	13		T35	36
transitions[0x1=>0x0]	12490	1			T41	17		T24	13		T35	36

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2541344	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	831	1			T24	3		T35	2		T36	71
all_pins[0]	transitions[0x0=>0x1]	614	1			T24	2		T35	1		T36	70
all_pins[0]	transitions[0x1=>0x0]	181	1			T41	6		T24	1		T35	4
all_pins[1]	values[0x0]	2541777	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	398	1			T41	6		T24	2		T35	5
all_pins[1]	transitions[0x0=>0x1]	297	1			T41	5		T24	2		T35	4
all_pins[1]	transitions[0x1=>0x0]	154	1			T35	2		T36	3		T37	3
all_pins[2]	values[0x0]	2541920	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	255	1			T41	1		T35	3		T36	4
all_pins[2]	transitions[0x0=>0x1]	203	1			T41	1		T35	3		T36	3
all_pins[2]	transitions[0x1=>0x0]	146	1			T41	3		T24	5		T35	7
all_pins[3]	values[0x0]	2541977	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	198	1			T41	3		T24	5		T35	7
all_pins[3]	transitions[0x0=>0x1]	153	1			T41	3		T24	4		T35	5
all_pins[3]	transitions[0x1=>0x0]	141	1			T41	2		T35	10		T37	1
all_pins[4]	values[0x0]	2541989	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	186	1			T41	2		T24	1		T35	12
all_pins[4]	transitions[0x0=>0x1]	153	1			T41	1		T24	1		T35	9
all_pins[4]	transitions[0x1=>0x0]	1616	1			T41	1		T24	2		T35	3
all_pins[5]	values[0x0]	2540526	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1649	1			T41	2		T24	2		T35	6
all_pins[5]	transitions[0x0=>0x1]	762	1			T41	2		T24	2		T35	5
all_pins[5]	transitions[0x1=>0x0]	9338	1			T41	4		T24	2		T35	4
all_pins[6]	values[0x0]	2531950	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	10225	1			T41	4		T24	2		T35	5
all_pins[6]	transitions[0x0=>0x1]	10162	1			T41	2		T24	2		T35	4
all_pins[6]	transitions[0x1=>0x0]	130	1			T41	1		T35	4		T36	2
all_pins[7]	values[0x0]	2541982	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	193	1			T41	3		T35	5		T36	3
all_pins[7]	transitions[0x0=>0x1]	142	1			T41	3		T35	5		T36	3
all_pins[7]	transitions[0x1=>0x0]	784	1			T24	3		T35	2		T36	71