Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15702

1

T15

6

T16

16

T17

10

auto[1]

10832

1

T13

14

T50

12

T60

14

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2802	1			T57	6		T56	16		T201	16
values[1]	3465	1			T52	8		T54	18		T120	10
values[2]	3114	1			T53	8		T59	2		T58	47
values[3]	3245	1			T238	6		T58	47		T36	36
values[4]	3294	1			T19	12		T60	14		T58	20
values[5]	3395	1			T13	14		T58	54		T118	8
values[6]	3580	1			T16	16		T51	10		T70	18
values[7]	3639	1			T15	6		T17	10		T20	14

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3337	1			T52	8		T55	14		T214	22
values[1]	3157	1			T53	8		T238	6		T58	109
values[2]	3051	1			T19	12		T70	18		T120	10
values[3]	3319	1			T51	10		T119	12		T48	81
values[4]	3861	1			T57	6		T59	2		T118	8
values[5]	3264	1			T13	14		T92	2		T60	14
values[6]	3167	1			T50	12		T58	20		T188	10
values[7]	3378	1			T15	6		T16	16		T17	10

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	171	1			T64	18		T65	9		T194	10
auto[0]	values[0]	values[1]	168	1			T65	20		T227	9		T180	8
auto[0]	values[0]	values[2]	285	1			T56	16		T64	18		T65	14
auto[0]	values[0]	values[3]	235	1			T284	68		T285	9		T286	13
auto[0]	values[0]	values[4]	176	1			T57	6		T48	18		T285	13
auto[0]	values[0]	values[5]	213	1			T36	12		T191	63		T227	14
auto[0]	values[0]	values[6]	164	1			T260	16		T180	14		T287	10
auto[0]	values[0]	values[7]	304	1			T256	16		T194	17		T114	13
auto[0]	values[1]	values[0]	268	1			T52	8		T214	22		T229	14
auto[0]	values[1]	values[1]	236	1			T58	58		T48	26		T83	4
auto[0]	values[1]	values[2]	214	1			T120	10		T48	10		T228	8
auto[0]	values[1]	values[3]	140	1			T288	6		T233	12		T285	12
auto[0]	values[1]	values[4]	446	1			T63	11		T265	14		T280	18
auto[0]	values[1]	values[5]	270	1			T89	20		T49	10		T65	15
auto[0]	values[1]	values[6]	307	1			T64	19		T236	54		T222	18
auto[0]	values[1]	values[7]	155	1			T54	18		T194	6		T289	6
auto[0]	values[2]	values[0]	182	1			T195	9		T222	8		T290	13
auto[0]	values[2]	values[1]	388	1			T53	8		T58	39		T63	13
auto[0]	values[2]	values[2]	253	1			T48	11		T254	20		T291	18
auto[0]	values[2]	values[3]	199	1			T248	12		T64	8		T249	9
auto[0]	values[2]	values[4]	299	1			T59	2		T227	8		T292	4
auto[0]	values[2]	values[5]	172	1			T86	6		T232	39		T249	14
auto[0]	values[2]	values[6]	145	1			T188	10		T195	6		T267	14
auto[0]	values[2]	values[7]	263	1			T61	10		T275	9		T262	22
auto[0]	values[3]	values[0]	353	1			T58	24		T293	16		T294	12
auto[0]	values[3]	values[1]	116	1			T238	6		T113	14		T180	15
auto[0]	values[3]	values[2]	126	1			T259	11		T233	10		T285	15
auto[0]	values[3]	values[3]	307	1			T189	20		T190	11		T71	32
auto[0]	values[3]	values[4]	249	1			T295	8		T286	8		T279	21
auto[0]	values[3]	values[5]	204	1			T215	10		T190	11		T266	20
auto[0]	values[3]	values[6]	346	1			T229	15		T244	12		T236	10
auto[0]	values[3]	values[7]	242	1			T36	10		T296	14		T71	23
auto[0]	values[4]	values[0]	184	1			T250	10		T180	20		T233	12
auto[0]	values[4]	values[1]	192	1			T48	16		T253	14		T193	12
auto[0]	values[4]	values[2]	222	1			T19	12		T58	5		T64	8
auto[0]	values[4]	values[3]	323	1			T48	16		T64	12		T219	16
auto[0]	values[4]	values[4]	316	1			T48	82		T180	12		T159	9
auto[0]	values[4]	values[5]	283	1			T199	8		T62	17		T150	23
auto[0]	values[4]	values[6]	140	1			T48	12		T240	6		T258	14
auto[0]	values[4]	values[7]	282	1			T62	13		T222	34		T114	8
auto[0]	values[5]	values[0]	273	1			T297	10		T236	12		T249	9
auto[0]	values[5]	values[1]	196	1			T276	6		T265	48		T222	11
auto[0]	values[5]	values[2]	165	1			T61	10		T262	8		T298	2
auto[0]	values[5]	values[3]	171	1			T61	11		T249	15		T222	28
auto[0]	values[5]	values[4]	359	1			T118	8		T61	18		T299	6
auto[0]	values[5]	values[5]	314	1			T58	47		T48	30		T246	24
auto[0]	values[5]	values[6]	280	1			T64	17		T61	16		T300	8
auto[0]	values[5]	values[7]	253	1			T48	17		T194	11		T262	52
auto[0]	values[6]	values[0]	207	1			T301	2		T265	8		T227	15
auto[0]	values[6]	values[1]	226	1			T236	11		T262	11		T195	6
auto[0]	values[6]	values[2]	287	1			T70	18		T94	15		T64	15
auto[0]	values[6]	values[3]	294	1			T51	10		T119	12		T48	8
auto[0]	values[6]	values[4]	102	1			T63	8		T49	6		T61	10
auto[0]	values[6]	values[5]	237	1			T302	2		T63	7		T275	9
auto[0]	values[6]	values[6]	243	1			T49	11		T236	13		T194	13
auto[0]	values[6]	values[7]	312	1			T16	16		T249	11		T262	12
auto[0]	values[7]	values[0]	325	1			T272	2		T190	11		T71	4
auto[0]	values[7]	values[1]	272	1			T64	17		T249	9		T113	18
auto[0]	values[7]	values[2]	163	1			T224	16		T65	13		T194	10
auto[0]	values[7]	values[3]	281	1			T220	166		T227	15		T150	19
auto[0]	values[7]	values[4]	435	1			T303	12		T62	18		T304	4
auto[0]	values[7]	values[5]	270	1			T92	2		T265	15		T227	9
auto[0]	values[7]	values[6]	169	1			T58	17		T305	4		T64	9
auto[0]	values[7]	values[7]	330	1			T15	6		T17	10		T20	14
auto[1]	values[0]	values[0]	229	1			T64	5		T65	17		T306	18
auto[1]	values[0]	values[1]	141	1			T65	2		T227	11		T261	20
auto[1]	values[0]	values[2]	90	1			T64	2		T65	6		T227	7
auto[1]	values[0]	values[3]	133	1			T285	15		T286	7		T307	14
auto[1]	values[0]	values[4]	116	1			T201	16		T48	2		T285	11
auto[1]	values[0]	values[5]	102	1			T36	8		T227	6		T287	8
auto[1]	values[0]	values[6]	179	1			T180	76		T287	10		T233	5
auto[1]	values[0]	values[7]	96	1			T194	3		T114	7		T233	8
auto[1]	values[1]	values[0]	122	1			T308	2		T66	20		T229	6
auto[1]	values[1]	values[1]	202	1			T58	4		T48	84		T236	5
auto[1]	values[1]	values[2]	248	1			T48	77		T193	17		T259	6
auto[1]	values[1]	values[3]	224	1			T84	16		T233	8		T285	9
auto[1]	values[1]	values[4]	251	1			T63	9		T265	90		T309	16
auto[1]	values[1]	values[5]	169	1			T49	10		T65	22		T190	7
auto[1]	values[1]	values[6]	144	1			T64	9		T236	10		T222	8
auto[1]	values[1]	values[7]	69	1			T194	14		T251	10		T310	19
auto[1]	values[2]	values[0]	160	1			T195	11		T222	31		T290	7
auto[1]	values[2]	values[1]	174	1			T58	8		T63	7		T64	10
auto[1]	values[2]	values[2]	194	1			T48	19		T291	113		T311	11
auto[1]	values[2]	values[3]	153	1			T64	12		T249	11		T222	11
auto[1]	values[2]	values[4]	158	1			T227	12		T239	27		T183	8
auto[1]	values[2]	values[5]	78	1			T249	6		T312	16		T285	12
auto[1]	values[2]	values[6]	114	1			T195	14		T233	8		T230	11
auto[1]	values[2]	values[7]	182	1			T271	22		T61	10		T313	10
auto[1]	values[3]	values[0]	167	1			T58	23		T229	12		T227	18
auto[1]	values[3]	values[1]	100	1			T113	6		T180	13		T183	13
auto[1]	values[3]	values[2]	190	1			T259	9		T233	10		T285	5
auto[1]	values[3]	values[3]	194	1			T190	12		T71	7		T259	9
auto[1]	values[3]	values[4]	138	1			T286	12		T279	19		T314	17
auto[1]	values[3]	values[5]	77	1			T190	18		T315	7		T290	13
auto[1]	values[3]	values[6]	272	1			T229	5		T236	10		T113	11
auto[1]	values[3]	values[7]	164	1			T36	26		T71	7		T194	7
auto[1]	values[4]	values[0]	120	1			T316	12		T180	10		T233	8
auto[1]	values[4]	values[1]	182	1			T48	4		T193	8		T287	7
auto[1]	values[4]	values[2]	196	1			T58	15		T64	12		T212	13
auto[1]	values[4]	values[3]	165	1			T48	16		T64	8		T212	9
auto[1]	values[4]	values[4]	198	1			T48	6		T180	63		T159	20
auto[1]	values[4]	values[5]	283	1			T60	14		T62	9		T150	23
auto[1]	values[4]	values[6]	96	1			T48	31		T180	6		T114	8
auto[1]	values[4]	values[7]	112	1			T62	7		T222	23		T114	12
auto[1]	values[5]	values[0]	197	1			T236	8		T249	11		T317	6
auto[1]	values[5]	values[1]	156	1			T265	7		T222	9		T223	5
auto[1]	values[5]	values[2]	112	1			T61	10		T262	12		T195	9
auto[1]	values[5]	values[3]	176	1			T61	9		T67	12		T249	5
auto[1]	values[5]	values[4]	170	1			T61	22		T71	24		T287	5
auto[1]	values[5]	values[5]	203	1			T13	14		T58	7		T48	10
auto[1]	values[5]	values[6]	118	1			T64	3		T61	4		T113	7
auto[1]	values[5]	values[7]	252	1			T48	23		T194	61		T262	7
auto[1]	values[6]	values[0]	204	1			T55	14		T200	4		T265	105
auto[1]	values[6]	values[1]	203	1			T236	26		T262	27		T195	14
auto[1]	values[6]	values[2]	155	1			T94	5		T64	5		T61	9
auto[1]	values[6]	values[3]	225	1			T48	41		T193	15		T262	34
auto[1]	values[6]	values[4]	95	1			T63	12		T49	14		T61	10
auto[1]	values[6]	values[5]	271	1			T63	13		T275	11		T249	8
auto[1]	values[6]	values[6]	286	1			T49	9		T236	9		T194	72
auto[1]	values[6]	values[7]	233	1			T249	9		T262	8		T311	5
auto[1]	values[7]	values[0]	175	1			T190	11		T71	24		T193	7
auto[1]	values[7]	values[1]	205	1			T64	3		T249	11		T113	22
auto[1]	values[7]	values[2]	151	1			T65	19		T194	10		T265	10
auto[1]	values[7]	values[3]	99	1			T227	5		T150	5		T318	12
auto[1]	values[7]	values[4]	353	1			T319	6		T62	23		T259	13
auto[1]	values[7]	values[5]	118	1			T265	5		T227	11		T320	20
auto[1]	values[7]	values[6]	164	1			T50	12		T58	3		T64	11
auto[1]	values[7]	values[7]	129	1			T229	14		T193	21		T194	12