Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	367	1			T20	4		T51	6		T119	4
auto[ReadAddrCrossIntoMailbox]	258	1			T20	2		T53	4		T94	2
auto[ReadAddrCrossOutOfMailbox]	259	1			T53	4		T58	4		T272	2
auto[ReadAddrCrossAllMailbox]	177	1			T20	2		T94	1		T48	2
auto[ReadAddrOutsideMailbox]	3134	1			T13	4		T17	4		T20	6

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2061

1

T13

2

T17

2

T20

7

auto[1]

2134

1

T13

2

T17

2

T20

7

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	711	1			T13	2		T17	2		T51	2
read_ops[0x0b]	696	1			T13	2		T20	4		T51	4
read_ops[0x3b]	720	1			T20	8		T53	6		T119	2
read_ops[0x6b]	713	1			T17	2		T94	1		T58	8
read_ops[0xbb]	669	1			T50	2		T51	2		T54	4
read_ops[0xeb]	686	1			T20	2		T52	2		T94	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T51	1		T238	1		T224	3
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	43	1			T51	1		T238	1		T48	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T53	1		T64	1		T193	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T53	1		T94	1		T275	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T58	1		T236	1		T113	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T63	1		T61	1		T249	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T64	1		T260	1		T287	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T94	1		T48	1		T63	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	239	1			T13	1		T17	1		T120	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T13	1		T17	1		T120	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T20	2		T51	1		T119	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T20	2		T51	1		T119	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T48	1		T65	2		T237	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T265	1		T223	2		T290	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T58	1		T65	1		T212	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T275	1		T260	1		T113	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T260	1		T262	1		T265	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T64	2		T260	1		T195	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	256	1			T13	1		T51	1		T54	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T13	1		T51	1		T54	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T119	1		T48	1		T276	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T119	1		T276	1		T269	2
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T20	1		T53	1		T193	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T20	1		T53	1		T249	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	38	1			T53	2		T48	2		T36	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T53	2		T260	1		T114	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T20	1		T48	1		T63	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T20	1		T64	1		T300	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	257	1			T20	2		T60	1		T56	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	269	1			T20	2		T60	1		T56	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T236	2		T265	1		T180	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T58	1		T48	1		T64	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T276	1		T230	1		T311	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T94	1		T48	1		T276	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T272	1		T36	1		T49	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T272	1		T64	1		T65	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T300	1		T259	1		T262	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T61	1		T300	1		T227	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	281	1			T17	1		T58	3		T201	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	270	1			T17	1		T58	4		T201	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T51	1		T58	1		T48	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T51	1		T199	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T236	1		T265	2		T180	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T62	1		T193	1		T236	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T58	1		T48	1		T64	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T49	1		T114	1		T233	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T229	1		T275	1		T259	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T62	1		T262	1		T233	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	233	1			T50	1		T54	2		T56	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	273	1			T50	1		T54	2		T94	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T224	2		T294	2		T258	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T224	2		T294	2		T258	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T63	1		T259	1		T262	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T265	1		T239	1		T230	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T259	1		T236	1		T265	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T58	1		T63	1		T249	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T258	1		T307	1		T321	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T64	1		T258	1		T262	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T20	1		T52	1		T55	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	255	1			T20	1		T52	1		T94	1