Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2735	1			T13	14		T20	14		T53	8
values[1]	2758	1			T16	16		T52	8		T54	18
values[2]	4280	1			T92	2		T58	62		T188	10
values[3]	3776	1			T17	10		T60	14		T58	40
values[4]	2794	1			T94	20		T58	47		T201	16
values[5]	2809	1			T19	12		T50	12		T57	6
values[6]	3587	1			T51	10		T120	10		T58	81
values[7]	3795	1			T15	6		T59	2		T56	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3588	1			T50	12		T51	10		T53	8
values[1]	3150	1			T17	10		T57	6		T56	16
values[2]	3636	1			T120	10		T58	54		T272	2
values[3]	3615	1			T13	14		T15	6		T16	16
values[4]	3095	1			T52	8		T70	18		T92	2
values[5]	2934	1			T19	12		T20	14		T58	82
values[6]	3177	1			T59	2		T60	14		T238	6
values[7]	3339	1			T188	10		T48	175		T63	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25798

1

T13

14

T15

6

T16

16

auto[1]

736

1

T50

2

T55

2

T58

3

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	199	1			T53	8		T319	6		T322	6
auto[0]	values[0]	values[1]	296	1			T323	8		T62	19		T244	12
auto[0]	values[0]	values[2]	372	1			T64	19		T61	16		T295	8
auto[0]	values[0]	values[3]	373	1			T13	14		T128	2		T180	74
auto[0]	values[0]	values[4]	393	1			T70	18		T302	2		T113	20
auto[0]	values[0]	values[5]	289	1			T20	14		T246	24		T194	18
auto[0]	values[0]	values[6]	255	1			T238	6		T296	14		T259	20
auto[0]	values[0]	values[7]	457	1			T219	16		T259	18		T249	19
auto[0]	values[1]	values[0]	453	1			T54	18		T214	22		T200	4
auto[0]	values[1]	values[1]	355	1			T190	28		T227	39		T155	4
auto[0]	values[1]	values[2]	347	1			T269	10		T265	77		T287	20
auto[0]	values[1]	values[3]	355	1			T16	16		T119	12		T55	12
auto[0]	values[1]	values[4]	247	1			T52	8		T48	31		T259	20
auto[0]	values[1]	values[5]	410	1			T48	40		T224	16		T61	19
auto[0]	values[1]	values[6]	291	1			T257	10		T324	35		T114	18
auto[0]	values[1]	values[7]	225	1			T63	19		T49	15		T61	20
auto[0]	values[2]	values[0]	798	1			T36	20		T300	8		T236	36
auto[0]	values[2]	values[1]	399	1			T276	6		T189	20		T61	18
auto[0]	values[2]	values[2]	532	1			T64	23		T222	18		T285	25
auto[0]	values[2]	values[3]	520	1			T48	48		T71	29		T259	18
auto[0]	values[2]	values[4]	518	1			T92	2		T64	18		T61	18
auto[0]	values[2]	values[5]	339	1			T58	62		T195	18		T325	2
auto[0]	values[2]	values[6]	467	1			T48	18		T297	10		T65	18
auto[0]	values[2]	values[7]	603	1			T188	10		T326	12		T83	4
auto[0]	values[3]	values[0]	479	1			T58	20		T48	29		T89	20
auto[0]	values[3]	values[1]	432	1			T17	10		T234	4		T64	20
auto[0]	values[3]	values[2]	285	1			T194	20		T274	14		T327	12
auto[0]	values[3]	values[3]	479	1			T63	19		T259	20		T222	38
auto[0]	values[3]	values[4]	420	1			T58	20		T48	20		T248	12
auto[0]	values[3]	values[5]	668	1			T64	27		T303	12		T220	166
auto[0]	values[3]	values[6]	451	1			T60	14		T229	18		T150	18
auto[0]	values[3]	values[7]	466	1			T232	39		T193	52		T194	18
auto[0]	values[4]	values[0]	249	1			T190	23		T328	20		T329	14
auto[0]	values[4]	values[1]	225	1			T58	45		T61	20		T62	26
auto[0]	values[4]	values[2]	336	1			T64	24		T262	31		T151	20
auto[0]	values[4]	values[3]	563	1			T67	8		T275	20		T113	20
auto[0]	values[4]	values[4]	399	1			T94	20		T271	22		T301	2
auto[0]	values[4]	values[5]	219	1			T201	16		T193	32		T249	19
auto[0]	values[4]	values[6]	480	1			T199	8		T240	6		T62	20
auto[0]	values[4]	values[7]	254	1			T227	20		T267	14		T114	20
auto[0]	values[5]	values[0]	213	1			T50	10		T195	20		T114	18
auto[0]	values[5]	values[1]	221	1			T57	6		T305	4		T193	28
auto[0]	values[5]	values[2]	517	1			T194	72		T262	57		T113	19
auto[0]	values[5]	values[3]	507	1			T258	14		T190	22		T71	38
auto[0]	values[5]	values[4]	287	1			T194	20		T291	20		T239	20
auto[0]	values[5]	values[5]	284	1			T19	12		T58	20		T61	19
auto[0]	values[5]	values[6]	233	1			T180	20		T330	2		T312	20
auto[0]	values[5]	values[7]	456	1			T48	172		T217	6		T239	95
auto[0]	values[6]	values[0]	488	1			T51	10		T194	100		T262	20
auto[0]	values[6]	values[1]	541	1			T64	20		T236	19		T249	20
auto[0]	values[6]	values[2]	650	1			T120	10		T58	53		T272	2
auto[0]	values[6]	values[3]	338	1			T49	20		T193	25		T249	20
auto[0]	values[6]	values[4]	505	1			T48	20		T64	20		T320	20
auto[0]	values[6]	values[5]	271	1			T48	20		T63	18		T233	18
auto[0]	values[6]	values[6]	497	1			T58	27		T48	20		T253	14
auto[0]	values[6]	values[7]	216	1			T192	8		T249	40		T265	38
auto[0]	values[7]	values[0]	632	1			T64	20		T229	19		T71	25
auto[0]	values[7]	values[1]	597	1			T56	16		T64	20		T61	18
auto[0]	values[7]	values[2]	504	1			T48	43		T65	47		T331	10
auto[0]	values[7]	values[3]	359	1			T15	6		T228	8		T190	27
auto[0]	values[7]	values[4]	229	1			T65	31		T180	31		T332	8
auto[0]	values[7]	values[5]	374	1			T48	88		T229	20		T71	69
auto[0]	values[7]	values[6]	412	1			T59	2		T36	33		T313	10
auto[0]	values[7]	values[7]	569	1			T229	20		T113	36		T266	20
auto[1]	values[0]	values[0]	7	1			T222	2		T333	2		T279	1
auto[1]	values[0]	values[1]	11	1			T62	1		T279	5		T334	2
auto[1]	values[0]	values[2]	18	1			T64	1		T61	4		T212	2
auto[1]	values[0]	values[3]	20	1			T180	1		T222	2		T287	1
auto[1]	values[0]	values[4]	20	1			T239	3		T290	2		T251	5
auto[1]	values[0]	values[5]	10	1			T194	2		T227	2		T285	2
auto[1]	values[0]	values[6]	3	1			T291	1		T251	2		-	-
auto[1]	values[0]	values[7]	12	1			T259	2		T249	1		T227	3
auto[1]	values[1]	values[0]	9	1			T262	1		T287	3		T335	2
auto[1]	values[1]	values[1]	8	1			T190	1		T227	1		T310	2
auto[1]	values[1]	values[2]	10	1			T265	2		T290	1		T307	1
auto[1]	values[1]	values[3]	12	1			T55	2		T66	2		T275	3
auto[1]	values[1]	values[4]	7	1			T48	1		T113	1		T231	1
auto[1]	values[1]	values[5]	11	1			T61	1		T194	2		T277	3
auto[1]	values[1]	values[6]	6	1			T114	2		T291	1		T290	3
auto[1]	values[1]	values[7]	12	1			T63	1		T49	5		T231	2
auto[1]	values[2]	values[0]	13	1			T236	1		T262	2		T315	1
auto[1]	values[2]	values[1]	4	1			T61	2		T336	1		T337	1
auto[1]	values[2]	values[2]	13	1			T222	2		T290	5		T338	3
auto[1]	values[2]	values[3]	20	1			T48	1		T71	1		T259	2
auto[1]	values[2]	values[4]	24	1			T64	2		T61	2		T265	2
auto[1]	values[2]	values[5]	7	1			T195	2		T339	5		-	-
auto[1]	values[2]	values[6]	12	1			T48	2		T65	2		T239	4
auto[1]	values[2]	values[7]	11	1			T236	1		T285	3		T223	1
auto[1]	values[3]	values[0]	8	1			T48	1		T65	2		T227	3
auto[1]	values[3]	values[1]	8	1			T265	1		T334	1		T340	3
auto[1]	values[3]	values[2]	9	1			T180	2		T222	4		T312	2
auto[1]	values[3]	values[3]	22	1			T63	1		T222	1		T233	2
auto[1]	values[3]	values[4]	7	1			T223	1		T314	1		T341	1
auto[1]	values[3]	values[5]	12	1			T64	1		T291	2		T341	1
auto[1]	values[3]	values[6]	17	1			T229	2		T150	5		T342	1
auto[1]	values[3]	values[7]	13	1			T194	2		T277	2		T160	1
auto[1]	values[4]	values[0]	6	1			T314	2		T343	1		T344	3
auto[1]	values[4]	values[1]	8	1			T58	2		T223	3		T318	3
auto[1]	values[4]	values[2]	11	1			T64	2		T279	1		T338	3
auto[1]	values[4]	values[3]	14	1			T67	4		T265	2		T160	1
auto[1]	values[4]	values[4]	8	1			T262	1		T345	2		T290	1
auto[1]	values[4]	values[5]	5	1			T193	1		T249	1		T262	1
auto[1]	values[4]	values[6]	14	1			T236	1		T195	1		T287	3
auto[1]	values[4]	values[7]	3	1			T237	2		T346	1		-	-
auto[1]	values[5]	values[0]	10	1			T50	2		T114	2		T291	1
auto[1]	values[5]	values[1]	10	1			T193	1		T261	6		T318	1
auto[1]	values[5]	values[2]	14	1			T262	2		T113	1		T265	2
auto[1]	values[5]	values[3]	12	1			T71	1		T265	2		T347	2
auto[1]	values[5]	values[4]	12	1			T312	2		T345	4		T348	4
auto[1]	values[5]	values[5]	10	1			T61	1		T349	6		T150	1
auto[1]	values[5]	values[6]	10	1			T160	4		T335	2		T350	4
auto[1]	values[5]	values[7]	13	1			T48	3		T239	4		T312	2
auto[1]	values[6]	values[0]	8	1			T194	1		T150	2		T351	1
auto[1]	values[6]	values[1]	17	1			T236	1		T180	5		T233	2
auto[1]	values[6]	values[2]	13	1			T58	1		T62	1		T236	1
auto[1]	values[6]	values[3]	7	1			T193	2		T239	1		T230	3
auto[1]	values[6]	values[4]	12	1			T183	3		T352	1		T343	2
auto[1]	values[6]	values[5]	7	1			T63	2		T233	2		T183	1
auto[1]	values[6]	values[6]	8	1			T190	4		T249	1		T239	1
auto[1]	values[6]	values[7]	9	1			T265	2		T180	3		T314	1
auto[1]	values[7]	values[0]	16	1			T229	1		T71	3		T275	2
auto[1]	values[7]	values[1]	18	1			T61	2		T236	1		T286	1
auto[1]	values[7]	values[2]	5	1			T65	1		T311	2		T160	1
auto[1]	values[7]	values[3]	14	1			T193	1		T290	1		T231	1
auto[1]	values[7]	values[4]	7	1			T65	1		T180	1		T161	3
auto[1]	values[7]	values[5]	18	1			T48	2		T71	5		T233	2
auto[1]	values[7]	values[6]	21	1			T36	3		T233	4		T286	2
auto[1]	values[7]	values[7]	20	1			T113	4		T312	1		T311	2