Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	865	1			T41	7		T24	10		T35	24
all_values[1]	865	1			T41	7		T24	10		T35	24
all_values[2]	865	1			T41	7		T24	10		T35	24
all_values[3]	865	1			T41	7		T24	10		T35	24
all_values[4]	865	1			T41	7		T24	10		T35	24
all_values[5]	865	1			T41	7		T24	10		T35	24
all_values[6]	865	1			T41	7		T24	10		T35	24
all_values[7]	865	1			T41	7		T24	10		T35	24

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3795

1

T41

32

T24

36

T35

100

auto[1]

3125

1

T41

24

T24

44

T35

92

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2736

1

T41

12

T24

32

T35

75

auto[1]

4184

1

T41

44

T24

48

T35

117

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3936

1

T41

30

T24

48

T35

108

auto[1]

2984

1

T41

26

T24

32

T35

84

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	183	1			T41	2		T24	2		T35	4
all_values[0]	auto[0]	auto[0]	auto[1]	96	1			T41	1		T24	3		T35	4
all_values[0]	auto[0]	auto[1]	auto[0]	134	1			T41	3		T35	7		T36	3
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T24	1		T36	1		T37	1
all_values[0]	auto[1]	auto[0]	auto[1]	190	1			T41	1		T24	1		T35	7
all_values[0]	auto[1]	auto[1]	auto[1]	174	1			T24	3		T35	2		T36	1
all_values[1]	auto[0]	auto[0]	auto[0]	186	1			T24	2		T35	4		T36	1
all_values[1]	auto[0]	auto[0]	auto[1]	92	1			T41	1		T24	2		T35	3
all_values[1]	auto[0]	auto[1]	auto[0]	141	1			T24	1		T35	5		T36	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T41	5		T24	1		T35	2
all_values[1]	auto[1]	auto[0]	auto[1]	222	1			T41	1		T24	3		T35	6
all_values[1]	auto[1]	auto[1]	auto[1]	145	1			T24	1		T35	4		T36	2
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T41	1		T24	2		T35	5
all_values[2]	auto[0]	auto[0]	auto[1]	70	1			T41	1		T24	2		T35	3
all_values[2]	auto[0]	auto[1]	auto[0]	152	1			T24	2		T35	7		T37	2
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T35	1		T36	2		T37	1
all_values[2]	auto[1]	auto[0]	auto[1]	209	1			T41	5		T24	3		T35	7
all_values[2]	auto[1]	auto[1]	auto[1]	190	1			T24	1		T35	1		T36	1
all_values[3]	auto[0]	auto[0]	auto[0]	179	1			T41	1		T35	2		T37	1
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T24	2		T35	4		T36	2
all_values[3]	auto[0]	auto[1]	auto[0]	138	1			T24	1		T35	7		T36	2
all_values[3]	auto[0]	auto[1]	auto[1]	86	1			T41	3		T24	3		T35	2
all_values[3]	auto[1]	auto[0]	auto[1]	206	1			T41	2		T35	7		T36	3
all_values[3]	auto[1]	auto[1]	auto[1]	164	1			T41	1		T24	4		T35	2
all_values[4]	auto[0]	auto[0]	auto[0]	163	1			T24	2		T35	1		T36	1
all_values[4]	auto[0]	auto[0]	auto[1]	101	1			T41	3		T24	1		T35	2
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T24	4		T35	3		T36	3
all_values[4]	auto[0]	auto[1]	auto[1]	74	1			T35	4		T179	3		T187	2
all_values[4]	auto[1]	auto[0]	auto[1]	229	1			T41	3		T35	4		T36	4
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T41	1		T24	3		T35	10
all_values[5]	auto[0]	auto[0]	auto[0]	282	1			T41	1		T24	1		T35	8
all_values[5]	auto[0]	auto[1]	auto[0]	220	1			T41	1		T24	5		T35	2
all_values[5]	auto[1]	auto[0]	auto[1]	208	1			T41	3		T24	1		T35	9
all_values[5]	auto[1]	auto[1]	auto[1]	155	1			T41	2		T24	3		T35	5
all_values[6]	auto[0]	auto[0]	auto[0]	176	1			T41	1		T24	2		T35	3
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T35	4		T36	2		T37	1
all_values[6]	auto[0]	auto[1]	auto[0]	137	1			T41	1		T24	2		T35	4
all_values[6]	auto[0]	auto[1]	auto[1]	93	1			T41	2		T35	1		T36	1
all_values[6]	auto[1]	auto[0]	auto[1]	196	1			T41	1		T24	4		T35	3
all_values[6]	auto[1]	auto[1]	auto[1]	184	1			T41	2		T24	2		T35	9
all_values[7]	auto[0]	auto[0]	auto[0]	191	1			T41	1		T24	1		T35	6
all_values[7]	auto[0]	auto[0]	auto[1]	88	1			T24	1		T35	1		T178	1
all_values[7]	auto[0]	auto[1]	auto[0]	156	1			T24	5		T35	7		T37	3
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T41	2		T35	2		T36	1
all_values[7]	auto[1]	auto[0]	auto[1]	194	1			T41	3		T24	1		T35	3
all_values[7]	auto[1]	auto[1]	auto[1]	155	1			T41	1		T24	2		T35	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal