Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1844

1

T5

1

T6

4

T26

16

auto[1]

1857

1

T5

1

T6

5

T14

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1962

1

T30

9

T31

13

T32

20

auto[1]

1739

1

T5

2

T6

9

T14

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2906

1

T5

2

T6

9

T14

1

auto[1]

795

1

T30

4

T31

4

T32

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	734	1			T6	4		T26	5		T28	2
valid[1]	731	1			T6	2		T26	7		T28	1
valid[2]	768	1			T5	1		T26	3		T28	3
valid[3]	709	1			T5	1		T6	1		T14	1
valid[4]	759	1			T6	2		T26	8		T28	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T32	1		T44	1		T94	4
auto[0]	auto[0]	valid[0]	auto[1]	161	1			T6	1		T26	3		T28	1
auto[0]	auto[0]	valid[1]	auto[0]	103	1			T31	2		T32	1		T22	1
auto[0]	auto[0]	valid[1]	auto[1]	175	1			T6	2		T26	1		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	129	1			T31	1		T32	3		T41	1
auto[0]	auto[0]	valid[2]	auto[1]	182	1			T5	1		T26	1		T28	2
auto[0]	auto[0]	valid[3]	auto[0]	113	1			T30	1		T31	1		T24	1
auto[0]	auto[0]	valid[3]	auto[1]	168	1			T26	6		T28	1		T90	3
auto[0]	auto[0]	valid[4]	auto[0]	115	1			T31	1		T32	1		T22	1
auto[0]	auto[0]	valid[4]	auto[1]	171	1			T6	1		T26	5		T28	1
auto[0]	auto[1]	valid[0]	auto[0]	117	1			T30	1		T32	1		T43	1
auto[0]	auto[1]	valid[0]	auto[1]	170	1			T6	3		T26	2		T28	1
auto[0]	auto[1]	valid[1]	auto[0]	124	1			T30	1		T31	2		T24	2
auto[0]	auto[1]	valid[1]	auto[1]	180	1			T26	6		T29	4		T90	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T30	1		T31	1		T24	1
auto[0]	auto[1]	valid[2]	auto[1]	164	1			T26	2		T28	1		T29	2
auto[0]	auto[1]	valid[3]	auto[0]	100	1			T32	2		T41	1		T43	2
auto[0]	auto[1]	valid[3]	auto[1]	182	1			T5	1		T6	1		T14	1
auto[0]	auto[1]	valid[4]	auto[0]	134	1			T30	1		T31	1		T32	4
auto[0]	auto[1]	valid[4]	auto[1]	186	1			T6	1		T26	3		T28	1
auto[1]	auto[0]	valid[0]	auto[0]	88	1			T30	2		T24	1		T43	1
auto[1]	auto[0]	valid[1]	auto[0]	78	1			T31	1		T32	1		T24	2
auto[1]	auto[0]	valid[2]	auto[0]	81	1			T31	1		T43	1		T360	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T94	2		T363	1		T367	2
auto[1]	auto[0]	valid[4]	auto[0]	77	1			T32	1		T24	1		T36	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T32	1		T43	2		T372	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T31	1		T32	1		T24	1
auto[1]	auto[1]	valid[2]	auto[0]	101	1			T32	1		T44	1		T94	1
auto[1]	auto[1]	valid[3]	auto[0]	64	1			T32	1		T198	1		T39	1
auto[1]	auto[1]	valid[4]	auto[0]	76	1			T30	2		T31	1		T32	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal